> -----Original Message-----
> From: Dasgupta, Romit 
> Sent: Friday, November 27, 2009 2:38 PM
> To: Premi, Sanjeev
> Cc: linux-omap@vger.kernel.org
> Subject: RE: omap3evm: touchscreen delays on pm branch
> 
> On Fri, 2009-11-27 at 14:11 +0530, Premi, Sanjeev wrote:
> > > -----Original Message-----
> > > From: Dasgupta, Romit 
> > > Sent: Friday, November 27, 2009 2:10 PM
> > > To: Premi, Sanjeev
> > > Cc: linux-omap@vger.kernel.org
> > > Subject: Re: omap3evm: touchscreen delays on pm branch
> > > 
> > > Premi, Sanjeev wrote:
> > > > Hi,
> > > > 
> > > > I am finding the response of touchscreen on the 
> omap3evm very slow.
> > > > 
> > > > Here is my test:
> > > > On console, I run : watch -n2 "cat /proc/interrupts"
> > > > Then, I tap the touchscreen approximately once per 
> second. However,
> > > > (usually) no interrupts are registered. As I increase 
> the frequency
> > > > of 'taps' more and more interrupts are registered. But still not
> > > > matching exact taps.
> > > > 
> > > > However, when I keep the cpu busy with "cat /dev/zero > 
> /dev/null &"
> > > > each tap is recognized.
> > > > 
> > > Do you see this even if we don't enable OFF?
> > > 
> > Yes. Sleep_while_idle=0; enable_off_mode=0
> > ~sanjeev
> 
> Hopefully you have the same TSC driver. Nevertheless, can you 
> please try
> this (just to see if clock domain idling is causing any 
> problem or not):

It is the same driver at SDP3430. I had earlier tried removing
cpuidle altogether and did not see this issue. I too believe that
issue is caused by clocks being going to (auto)idle.

But then, Hemanth should be seeing the same behavior.

~sanjeev

> 
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c 
> b/arch/arm/mach-omap2/cpuidle34xx.c
> index 1cfa5a6..79710a1 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -248,7 +248,8 @@ void omap_init_power_states(void)
>                       cpuidle_params_table[OMAP3_STATE_C2].threshold;
>       omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
>       omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
> -     omap3_power_states[OMAP3_STATE_C2].flags = 
> CPUIDLE_FLAG_TIME_VALID;
> +     omap3_power_states[OMAP3_STATE_C2].flags = 
> CPUIDLE_FLAG_TIME_VALID |
> +                             CPUIDLE_FLAG_CHECK_BM;
>  
>       /* C3 . MPU CSWR + Core inactive */
>       omap3_power_states[OMAP3_STATE_C3].valid =
> 
> 

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