Paul Walmsley said the following on 12/02/2009 03:33 AM: > The code that reprograms the SDRC memory controller during CORE DVFS, > mach-omap2/sram34xx.S:omap3_sram_configure_core_dpll(), does not > ensure that all L3 initiators are prevented from accessing the SDRAM > before modifying the SDRC AC timing and MR registers. This can cause > memory to be corrupted or cause the SDRC to enter an unpredictable > state. This patch comments out that code for now and adds a note > explaining what is going on. Ideally it can be added back in once > supporting code is present to ensure that other initiators aren't > touching the SDRAM. At the very least, these registers should be > reprogrammable during kernel init to deal with buggy bootloaders. > > This is a modification of a patch originally written by Rajendra Nayak > <[email protected]> (the original is at http://patchwork.kernel.org/patch/51927/). > Rather than removing the code completely, this patch just comments it out. > why not make this a #ifdef instead if we need it some other time, a #if 0 and it's intention might not be readable without doing a git annotate in a few months time.. > Thanks to Benoît Cousson <[email protected]> and Christophe Sucur > <[email protected]> for explaining the technical basis for this and for > explaining what can be done to make this path work in future code. > Thanks to Richard Woodruff <[email protected]> for his comments. > > Signed-off-by: Paul Walmsley <[email protected]> > Cc: Rajendra Nayak <[email protected]> > Cc: Christophe Sucur <[email protected]> > Cc: Benoît Cousson <[email protected]> > Cc: Richard Woodruff <[email protected]> > --- > arch/arm/mach-omap2/sram34xx.S | 18 ++++++++++++++++-- > 1 files changed, 16 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S > index 82aa4a3..8fa8955 100644 > --- a/arch/arm/mach-omap2/sram34xx.S > +++ b/arch/arm/mach-omap2/sram34xx.S > @@ -91,8 +91,18 @@ > * new SDRC_ACTIM_CTRL_B_1 register contents > * new SDRC_MR_1 register value > * > - * If the param SDRC_RFR_CTRL_1 is 0, the parameters > - * are not programmed into the SDRC CS1 registers > + * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into > + * the SDRC CS1 registers > + * > + * NOTE: This code no longer attempts to program the SDRC AC timing and MR > + * registers. This is because the code currently cannot ensure that all > + * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the > + * SDRAM when the registers are written. If the registers are changed while > + * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC > + * may enter an unpredictable state. The code to reprogram the registers, > + * however, has been left in -- commented out in "#if 0" .. "#endif" blocks > -- > + * since in the future, the intent is to re-enable this code in cases where > we > + * can ensure that no initiators are touching the SDRAM. > */ > ENTRY(omap3_sram_configure_core_dpll) > stmfd sp!, {r1-r12, lr} @ store regs to stack > @@ -219,6 +229,7 @@ configure_sdrc: > ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM > ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM > str r12, [r11] @ store > +#if 0 > ldr r12, omap_sdrc_actim_ctrl_a_0_val > ldr r11, omap3_sdrc_actim_ctrl_a_0 > str r12, [r11] > @@ -228,11 +239,13 @@ configure_sdrc: > ldr r12, omap_sdrc_mr_0_val > ldr r11, omap3_sdrc_mr_0 > str r12, [r11] > +#endif > ldr r12, omap_sdrc_rfr_ctrl_1_val > cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0, > beq skip_cs1_prog @ do not program cs1 params > ldr r11, omap3_sdrc_rfr_ctrl_1 > str r12, [r11] > +#if 0 > ldr r12, omap_sdrc_actim_ctrl_a_1_val > ldr r11, omap3_sdrc_actim_ctrl_a_1 > str r12, [r11] > @@ -242,6 +255,7 @@ configure_sdrc: > ldr r12, omap_sdrc_mr_1_val > ldr r11, omap3_sdrc_mr_1 > str r12, [r11] > +#endif > skip_cs1_prog: > ldr r12, [r11] @ posted-write barrier for SDRC > bx lr >
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