> -----Original Message----- > From: Paul Walmsley [mailto:p...@pwsan.com] > Sent: Thursday, April 01, 2010 2:46 PM > To: Sripathy, Vishwanath > Cc: linux-omap@vger.kernel.org > Subject: Re: [PATCHV3 0/2] MPU/IVA bypass clock configuration > > Hi Vishwanath, > > On Thu, 1 Apr 2010, Vishwanath BS wrote: > > > DSP usage at VDD1 OPP1 and OPP2 with Smartreflex enabled and any MM > > UCs running DSP codec was earlier restricted as DSP crashed. > > The root cause is wrong DPLL1/DPLL2 Bypass clock at VDD1 OPP1 and OPP2. > > The solution is to make sure DPLL1/DPLL2 bypass clock is always less > > than maximum supported frequency for the specific OPP. > > Typically these settings are to be done in bootloaders. > > > > All the patches have been tested on OMAP3630 ZOOM3 platform. > > Comments adressed in V3: > > 1. Used clk_set_rate API instead of directly writing to registers > > 2. Split the patch into 2 patches. > > > > Vishwanath BS (4): > > OMAP3: Set MPU and IVA bypass Clock Divider > > OMAP3 PM: Set MPU and IVA bypass clock dividers in DVFS > > On what tree do these patches apply? I have applied them on top of wip_opp branch in Kevin's PM branch. Regards Vishwa
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