To calculate the dpll3 M2 clock stabilization delay dynamically and wait
time for L3 M2 clock stabilization are different for 3430 & 3630 and is
as follows:
3430: 4*REFCLK + 8*CLKOUTX2
3630: 2*SYS_CLK + 10*CLKOUTX2
REFCLK & CLKOUTX2 are derived from M, N, M2  and DPLL reference clock.

Incase of 3430 a 2usec and 3630 1usec buffer time is added for safety.

Signed-off-by: Pramod Gurav <pramod.gu...@ti.com>
Signed-off-by: Vishwanath Sripathy <vishwanath...@ti.com>
Signed-off-by: Ambresh K <ambr...@ti.com>

---
 arch/arm/mach-omap2/clkt34xx_dpll3m2.c |   27 +++++++++++++++++++++------
 1 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c 
b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 6ad18f2..af0807a 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -39,6 +39,12 @@
 #define                SHIFT_DPLL_M            16
 #define                SHIFT_DPLL_N            8
 #define                SHIFT_DPLL_M2           27
+
+/*
+ * While calculating M2 stabilization delay, especially the formula
+ * used for 3630 computes to zero. So to avoid calculation truncating to
+ * zero, SCALING_FACTOR is used appropriately.
+ */
 #define                SCALING_FACTOR          10
 
 /*
@@ -107,12 +113,21 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned 
long rate)
        sys_clk = (1 << SCALING_FACTOR) / sys_clk_rate;
        clkoutx2 = (sys_clk * (n + 1) * m2) / (2 * m);
 
-       /* wait time for L3 clk stabilization = 4*REFCLK + 8*CLKOUTX2 */
-       refclk = (n + 1) * sys_clk;
-       switch_latency =  (4 * refclk) + (8 * clkoutx2);
-
-       /* Adding 2000 ns to sdrc clk stab */
-       sdrc_clk_stab =  switch_latency + 2000;
+       /*
+        * wait time for L3 clk stabilization
+        * for OMAP3430 = 4*REFCLK + 8*CLKOUTX2
+        * for OMAP3630 = 2*REFCLK + 8*CLKOUTX2
+        */
+       if (cpu_is_omap3630()) {
+               switch_latency = (2 * sys_clk) + (10 * clkoutx2);
+               /* Adding 1000 nano seconds to sdrc clk stab */
+               sdrc_clk_stab = switch_latency + 1000;
+       } else {
+               refclk = (n + 1) * sys_clk;
+               switch_latency =  (4 * refclk) + (8 * clkoutx2);
+               /* Adding 2000 ns to sdrc clk stab */
+               sdrc_clk_stab =  switch_latency + 2000;
+       }
 
        /*
         * Calculate the number of MPU cycles
-- 
1.6.0.4

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