On Wed, May 2, 2012 at 4:25 PM, Bedia, Vaibhav <vaibhav.be...@ti.com> wrote:
> On Wed, May 02, 2012 at 15:48:01, Shilimkar, Santosh wrote:
>> On Wed, May 2, 2012 at 3:40 PM, Bedia, Vaibhav <vaibhav.be...@ti.com> wrote:
>> > Hi Tero,
>> >
>> > On Fri, Apr 20, 2012 at 15:03:34, Kristo, Tero wrote:
>> >> From: Rajendra Nayak <rna...@ti.com>
>> >>
[...]
>>
>> [...]
>> >> +void omap4_dpll_resume_off(void)
>> >> +{
>> >> + u32 i;
>> >> + struct omap4_dpll_regs *dpll_reg = dpll_regs;
>> >> +
>> >> + for (i = 0; i < ARRAY_SIZE(dpll_regs); i++, dpll_reg++) {
>> >> + omap4_dpll_restore_reg(dpll_reg, &dpll_reg->clksel);
>> >> + omap4_dpll_restore_reg(dpll_reg, &dpll_reg->div_m2);
>> >> + omap4_dpll_restore_reg(dpll_reg, &dpll_reg->div_m3);
>> >> + omap4_dpll_restore_reg(dpll_reg, &dpll_reg->div_m4);
>> >> + omap4_dpll_restore_reg(dpll_reg, &dpll_reg->div_m5);
>> >> + omap4_dpll_restore_reg(dpll_reg, &dpll_reg->div_m6);
>> >> + omap4_dpll_restore_reg(dpll_reg, &dpll_reg->div_m7);
>> >> + omap4_dpll_restore_reg(dpll_reg, &dpll_reg->clkdcoldo);
>> >> +
>> >> + /* Restore clkmode after the above registers are restored */
>> >> + omap4_dpll_restore_reg(dpll_reg, &dpll_reg->clkmode);
>> >> +
>> >> + omap4_wait_dpll_lock(dpll_reg);
>> >> +
>> >> + /* Restore autoidle settings after the dpll is locked */
>> >> + omap4_dpll_restore_reg(dpll_reg, &dpll_reg->autoidle);
>> >> + }
>> >> +}
>> >
>> > If this function is placed in SRAM and PER PLL restored just after MPU
>> > won't the exit latency be further optimized?
>> >
>> How ?
>> SRAM is sower memory than DDR so I don't see how it
>> will reduce latency.
>>
>
> I am just guessing if that's indeed the case ;)
> Haven't done any measurements to really check if that's indeed the case
> though.
>
You don't have to do any real measurements at least on OMAP.
OCMC RAM is interfaced over L4 and MPU has to cross two interconnect
bridges to reach to SRAM. DDR is more of direct path and much faster.
Regards
Santosh
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