On Wed, May 2, 2012 at 5:10 PM, Bedia, Vaibhav <vaibhav.be...@ti.com> wrote: > On Wed, May 02, 2012 at 16:30:26, Shilimkar, Santosh wrote: > [...] > >> >> How ? >> >> SRAM is sower memory than DDR so I don't see how it >> >> will reduce latency. >> >> >> > >> > I am just guessing if that's indeed the case ;) >> > Haven't done any measurements to really check if that's indeed the case >> > though. >> > >> You don't have to do any real measurements at least on OMAP. >> OCMC RAM is interfaced over L4 and MPU has to cross two interconnect >> bridges to reach to SRAM. DDR is more of direct path and much faster. >> > > Hmm, I was under the impression that OCMC RAM was on L3, at least for OMAP4. Nope. It's on L4 and it is same for all OMAPs including OMAP5
> Maybe there's a extra low latency path for DDR that I am missing. Even OMAP3 DDR is faster than OCMC RAM. Regards Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
