On Tuesday 06 August 2013 01:49 PM, Dave Gerlach wrote: > From: Vaibhav Bedia <[email protected]> > > SDRAM controller on AM33XX requires that a modification of certain > bit-fields in PWR_MGMT_CTRL register (ref. section 7.3.5.13 in > AM335x-Rev H) is followed by a dummy read access to SDRAM. This > scenario arises when entering a low power state like DeepSleep. > To ensure that the read is not from a cached region we reserve > some memory during bootup using the arm_memblock_steal() API. > > A subsequent patch will pass along the location of the reserved > memory location to the AM335x suspend handler which modifies the > PWR_MGMT_CTRL register in the EMIF. > > Signed-off-by: Vaibhav Bedia <[email protected]> > Signed-off-by: Dave Gerlach <[email protected]> > --- Acked-by: Santosh Shilimkar <[email protected]>
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