Hi all,
I am starting to deal with performance registers on an Intel core
i5-2520M dual core (and hyperthreaded) processor. In this context I
reached the CPUID x86 instruction. Playing with this instruction I am
able to get some information about my cpu performance monitoring unit.
According to this instruction my Last-level cache misses event is available.
My question is about the link between events reported in Intel
documentation and events listed by perf list. Is the perf list
cache-misses event the same than the one mentioned as Last-level cache
missesin Intel documentation ?
Thanks,
--------
Manu
--
To unsubscribe from this list: send the line "unsubscribe linux-perf-users" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
