Roland Dreier wrote:
> T4 EQ entries are in multiples of 64B. Currently the RDMA SQ and RQ
> use fixed sized entries composed of 4 EQ entries for the SQ and 2 EQ
> entries for the RQ. For optimial latency with small IO, we need to
> change this so the HW only needs to DMA the EQ entries actually used by
> a given work request.
This seems not to be a fix, just an optimization -- so at this point for
2.6.36 I think. Or am I wrong?
You are correct...I was hoping since iw_cxgb4 is new to 2.6.35, we could
still get this in.
But if you disagree, then 2.6.36...
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