Re: spi-rspi mixes DMA and PIO transfers causing PIO transfer to fail.

[Daniel Palmer]

On 5 August 2016 at 03:46, Geert Uytterhoeven <ge...@linux-m68k.org> wrote:

>     Performance figures for reading from a QSPI FLASH driven at 24.375 MHz
>     on r8a7791/koelsch:
>       - Single:  1.1 Mbps PIO, 23 Mbps DMA
>       - Dual  : 12.7 Mbps PIO, 48 Mbps DMA
>       - Quad  : 13   Mbps PIO, 70 Mbps DMA

Thanks for those numbers. I have something to aim for now. :)
What I'm seeing on my logic analyser with the bus at 10MHz is 8 clocks
taking ~500ns,
~1700ns of idle and then 8 more clocks. spi-rpi doesn't seem to set
any of the registers
for adding in delays so I guess it's to do with the DMA controller.

Cheers,

Daniel