Re: spi-rspi mixes DMA and PIO transfers causing PIO transfer to fail.

[Daniel Palmer]

I tried it out. Not a massive difference but at 10MHz (in reality
~8.6MHz) the delay between bytes goes from 1.36us down to 1.24us.
I didn't notice this before as I was looking at much longer buffer
being written and couldn't see CS go high again but if I write 32
bytes of data that is complete in ~80us but the chip select is held
low for 2ms after that. I think that's probably a bigger issue than
the delay between bytes. :)