Defines the bits controlling FIFO thresholds, adds the additional HSCIF registers to the register map.
Signed-off-by: Ulrich Hecht <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> --- drivers/tty/serial/sh-sci.c | 2 ++ drivers/tty/serial/sh-sci.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index db5de80..3a9c001 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -377,6 +377,8 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [SCPDR] = sci_reg_invalid, [SCDL] = { 0x30, 16 }, [SCCKS] = { 0x34, 16 }, + [HSRTRGR] = { 0x54, 16 }, + [HSTTRGR] = { 0x58, 16 }, }, /* diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h index ffa6d68..2c45e79 100644 --- a/drivers/tty/serial/sh-sci.h +++ b/drivers/tty/serial/sh-sci.h @@ -29,6 +29,8 @@ enum { SCPDR, /* Serial Port Data Register */ SCDL, /* BRG Frequency Division Register */ SCCKS, /* BRG Clock Select Register */ + HSRTRGR, /* Rx FIFO Data Count Trigger Register */ + HSTTRGR, /* Tx FIFO Data Count Trigger Register */ SCIx_NR_REGS, }; @@ -99,6 +101,10 @@ enum { #define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK)) /* SCFCR (FIFO Control Register) */ +#define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */ +#define SCFCR_RTRG0 BIT(6) +#define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */ +#define SCFCR_TTRG0 BIT(4) #define SCFCR_MCE BIT(3) /* Modem Control Enable */ #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */ #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */ -- 2.7.4
