Hi Kaneko-san, Kihara-san,
On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko <[email protected]> wrote:
> From: Takeshi Kihara <[email protected]>
>
> This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment
> for SSI pins group.
>
> This is a correction to the incorrect implementation of MOD_SEL register
> pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
> User's Manual Rev.0.51E or later.
>
> Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
> Signed-off-by: Takeshi Kihara <[email protected]>
> Signed-off-by: Yoshihiro Kaneko <[email protected]>
> ---
> drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 38
> ++++++++++++++++++------------------
> 1 file changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
> index 4d070c2..18c9c61 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
> @@ -1277,7 +1277,7 @@ enum {
> PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
> PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
> PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
> - PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
> + PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
The SSI_SCK2_A part seems to have been removed in Rev.052E and later?
However, I can't find that in the errata for Rev.051E.
> PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
> PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
> PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B,
> SEL_TIMER_TMU_1),
The rest looks good to me.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
