From: Hiromitsu Yamasaki <[email protected]> Reset register before starting transfer.
Signed-off-by: Hiromitsu Yamasaki <[email protected]> Signed-off-by: Dirk Behme <[email protected]> --- drivers/spi/spi-sh-msiof.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index fdad8d852602..e8aebd406477 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -130,6 +130,8 @@ struct sh_msiof_spi_priv { #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ #define CTR_TXE 0x00000200 /* Transmit Enable */ #define CTR_RXE 0x00000100 /* Receive Enable */ +#define CTR_TXRST 0x00000002 /* Transmit Reset */ +#define CTR_RXRST 0x00000001 /* Receive Reset */ /* FCTR */ #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */ @@ -254,6 +256,25 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data) return IRQ_HANDLED; } +static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p) +{ + u32 mask = CTR_TXRST | CTR_RXRST; + u32 data; + int k; + + data = sh_msiof_read(p, CTR); + data |= mask; + + sh_msiof_write(p, CTR, data); + + for (k = 100; k > 0; k--) { + if (!(sh_msiof_read(p, CTR) & mask)) + break; + + udelay(10); + } +} + static struct { unsigned short div; unsigned short brdv; @@ -924,6 +945,9 @@ static int sh_msiof_transfer_one(struct spi_master *master, bool swab; int ret; + /* reset registers */ + sh_msiof_spi_reset_regs(p); + /* setup clocks (clock already enabled in chipselect()) */ if (!spi_controller_is_slave(p->master)) sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); -- 2.14.1
