On Wed, May 23, 2018 at 11:02:04AM +0200, Geert Uytterhoeven wrote:
> According to section 59.2.4 MSIOF Receive Mode Register 1 (SIRMDR1) in
> the R-Car Gen3 datasheet Rev.1.00, the value of the SIRMDR1.SYNCAC bit
> must match the value of the SITMDR1.SYNCAC bit. However,
> sh_msiof_spi_setup() changes only the latter.
>
> Fix this by updating the SIRMDR1 register like the SITMDR1 register,
> taking into account register bits that exist in SITMDR1 only.
>
> Reported-by: Renesas BSP team via Yoshihiro Shimoda
> <yoshihiro.shimoda...@renesas.com>
> Fixes: 7ff0b53c4051145d ("spi: sh-msiof: Avoid writing to registers from
> spi_master.setup()")
> Signed-off-by: Geert Uytterhoeven <geert+rene...@glider.be>
Reviewed-by: Simon Horman <horms+rene...@verge.net.au>
> ---
> drivers/spi/spi-sh-msiof.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
> index 244e841fc4bcfcc7..09c04c1b7d0b5a15 100644
> --- a/drivers/spi/spi-sh-msiof.c
> +++ b/drivers/spi/spi-sh-msiof.c
> @@ -567,14 +567,16 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
>
> /* Configure native chip select mode/polarity early */
> clr = MDR1_SYNCMD_MASK;
> - set = MDR1_TRMD | TMDR1_PCON | MDR1_SYNCMD_SPI;
> + set = MDR1_SYNCMD_SPI;
> if (spi->mode & SPI_CS_HIGH)
> clr |= BIT(MDR1_SYNCAC_SHIFT);
> else
> set |= BIT(MDR1_SYNCAC_SHIFT);
> pm_runtime_get_sync(&p->pdev->dev);
> tmp = sh_msiof_read(p, TMDR1) & ~clr;
> - sh_msiof_write(p, TMDR1, tmp | set);
> + sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
> + tmp = sh_msiof_read(p, RMDR1) & ~clr;
> + sh_msiof_write(p, RMDR1, tmp | set);
> pm_runtime_put(&p->pdev->dev);
> p->native_cs_high = spi->mode & SPI_CS_HIGH;
> p->native_cs_inited = true;
> --
> 2.7.4
>
