On Mon, Nov 05, 2018 at 11:32:37AM +0100, jacopo mondi wrote:
> Hi Simon,
> 
> On Wed, Oct 31, 2018 at 03:37:39PM +0100, Simon Horman wrote:
> > On Wed, Oct 31, 2018 at 02:18:40PM +0100, jacopo mondi wrote:
> > > Hi Simon,
> > >
> > > On Wed, Oct 31, 2018 at 01:48:13PM +0100, Simon Horman wrote:
> > > > On Tue, Oct 30, 2018 at 02:57:59PM +0200, Laurent Pinchart wrote:
> > > > > Hi Jacopo,
> > > > >
> > > > > On Tuesday, 30 October 2018 12:14:31 EET jacopo mondi wrote:
> > > > > > On Mon, Sep 10, 2018 at 05:12:30PM +0300, Laurent Pinchart wrote:
> > > > > > > On Wednesday, 5 September 2018 18:29:43 EEST Jacopo Mondi wrote:
> > > > > > >> From: Koji Matsuoka <[email protected]>
> > > > > > >>
> > > > > > >> Add device nodes for VIN4, VIN5 and CSI40 to R-Car E3 R8A77990 
> > > > > > >> device
> > > > > > >> tree.
> > > > > > >>
> > > > > > >> Signed-off-by: Koji Matsuoka <[email protected]>
> > > > > > >> Signed-off-by: Takeshi Kihara <[email protected]>
> > > > > > >> Signed-off-by: Jacopo Mondi <[email protected]>
> > > > > > >> ---
> > > > > > >>
> > > > > > >>  arch/arm64/boot/dts/renesas/r8a77990.dtsi | 79 
> > > > > > >> ++++++++++++++++++++++++
> > > > > > >>  1 file changed, 79 insertions(+)
> > > > > > >>
> > > > > > >> diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > > > > >> b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 
> > > > > > >> ae89260..0ae7bbe
> > > > > > >> 100644
> > > > > > >> --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > > > > >> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > > > > >> @@ -337,6 +337,85 @@
> > > > > > >>
> > > > > > >>                          status = "disabled";
> > > > > > >>
> > > > > > >>                  };
> > > > > > >>
> > > > > > >> +                csi40: csi2@feaa0000 {
> > > > > > >
> > > > > > > I believe Simon would like to keep the nodes sorted by address
> > > > > > >
> > > > > > >> +                        compatible = "renesas,r8a77990-csi2", 
> > > > > > >> "renesas,rcar-gen3-csi2";
> > > > > > >> +                        reg = <0 0xfeaa0000 0 0x10000>;
> > > > > > >
> > > > > > > 0x10000 seems pretty large to me.
> > > > > >
> > > > > > It seems to me that all Gen3 SoC have this lenght specified
> > > > > >
> > > > > > $git grep -A 10 'csi[2|4][0|1]: csi' arch/arm64/boot/dts/renesas/ | 
> > > > > > grep reg
> > > > > > arch/arm64/boot/dts/renesas/r8a7795.dtsi-    reg = <0 0xfea80000 0 
> > > > > > 0x10000>;
> > > > > > arch/arm64/boot/dts/renesas/r8a7795.dtsi-    reg = <0 0xfeaa0000 0 
> > > > > > 0x10000>;
> > > > > > arch/arm64/boot/dts/renesas/r8a7795.dtsi-    reg = <0 0xfeab0000 0 
> > > > > > 0x10000>;
> > > > > > arch/arm64/boot/dts/renesas/r8a7796.dtsi-    reg = <0 0xfea80000 0 
> > > > > > 0x10000>;
> > > > > > arch/arm64/boot/dts/renesas/r8a7796.dtsi-    reg = <0 0xfeaa0000 0 
> > > > > > 0x10000>;
> > > > > > arch/arm64/boot/dts/renesas/r8a77965.dtsi-   reg = <0 0xfea80000 0 
> > > > > > 0x10000>;
> > > > > > arch/arm64/boot/dts/renesas/r8a77965.dtsi-   reg = <0 0xfeaa0000 0 
> > > > > > 0x10000>;
> > > > > > arch/arm64/boot/dts/renesas/r8a77970.dtsi-   reg = <0 0xfeaa0000 0 
> > > > > > 0x10000>;
> > > > > > arch/arm64/boot/dts/renesas/r8a77980.dtsi-   reg = <0 0xfeaa0000 0 
> > > > > > 0x10000>;
> > > > > > arch/arm64/boot/dts/renesas/r8a77980.dtsi-   reg = <0 0xfeab0000 0 
> > > > > > 0x10000>;
> > > > > > arch/arm64/boot/dts/renesas/r8a77990.dtsi-   reg = <0 0xfeaa0000 0 
> > > > > > 0x10000>;
> > > > > >
> > > > > > Am I missing something?
> > > > >
> > > > > Cargo-cult programming ? :-) This will likely not hurt, but such a 
> > > > > large
> > > > > memory area is not required, and we'll save a bit of memory if we 
> > > > > reduce the
> > > > > mapping from 64kB to 4kB (or less)
> > > >
> > > > Can we please update this patch, and existing dtsi files,
> > > > to use an appropriately small register window?
> > > >
> > >
> > > What if we keep this one as it is and we change all the DTSIs in one
> > > go?
> >
> > I would rather we correct this patch than add it with a known problem.
> 
> Sorry, I was confused. This patch is already in v4.20.
> 
> If we want to fix this, a single follow-up patch that changes the
> memory area size for all SoCs is required.

Thanks, I was also confused.

Your proposal sounds good to me.

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