On 05/07/2019 04:15 PM, Tudor Ambarus wrote:
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 73172d7f512b..b94a6eaaaca5 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1551,6 +1551,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor
> *nor)
> u8 sr_cr[2];
> int ret;
>
> + dev_err(dev, "%s\n", __FUNCTION__);
> /* Check current Quad Enable bit value. */
> ret = read_cr(nor);
> if (ret < 0) {
> @@ -3911,6 +3912,12 @@ static int spi_nor_setup(struct spi_nor *nor,
> static int spi_nor_init(struct spi_nor *nor)
> {
> int err;
> + u8 val;
> + u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
> +
> + /* Check current Quad Enable bit value. */
> + val = read_cr(nor);
this should have been:
val = read_sr(nor);
sorry.
> + dev_err(nor->dev, "%s val = %02x\n", val);
and here
dev_err(nor->dev, "%s val = %02x\n", __FUNCTION__, val);
>
> /*
> * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
> @@ -3921,7 +3928,7 @@ static int spi_nor_init(struct spi_nor *nor)
> JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
> nor->info->flags & SPI_NOR_HAS_LOCK) {
> write_enable(nor);
> - write_sr(nor, 0);
> + write_sr(nor, val & ~mask);
> spi_nor_wait_till_ready(nor);
> }
>
