Hi, Geert, On 05/09/2019 02:12 PM, Geert Uytterhoeven wrote: > External E-Mail > > > Hi Tudor, > > On Thu, May 9, 2019 at 12:31 PM <[email protected]> wrote: >> On 05/09/2019 12:11 PM, Geert Uytterhoeven wrote: >>> On Thu, May 9, 2019 at 8:56 AM <[email protected]> wrote: >>>> When the configuration register QUAD bit CR[1] is 1, only the WRR command >>>> format >>>> with 16 data bits may be used, WRR with 8 bits is not recognized and hence >>>> the >>>> FFs. You probably set quad bit in u-boot, while others don't. We can >>>> verify this >>>> assumption with the patch form below. Can you try it? >>> >>> And /dev/mtd0 reading works fine. >>> Thanks! >>> >> >> I'm glad that it worked, thanks for the help. I'll do a patch to fix this >> case, >> but probably it will qualify for -next. Is -next ok for you? > > Given the issue is present only in -next, fixing it in -next is fine for me. > Thanks! >
I've started working to squash the bug discovered by this patch. spi-nor flashes from different manufacturers have widely different configurations for status and configuration registers. I have a work in progress patch, backward compatibility requirements increased code complexity. I'll be out of office and will return on 3rd of June. Probably I will not finish it today, this is to inform you (and others) that I'll be inactive next week. Cheers, ta
