Hi Tudor,

On 09/05/19 4:01 PM, tudor.amba...@microchip.com wrote:
[...]
>>
>>> --- a/drivers/mtd/spi-nor/spi-nor.c
>>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>>
>>> +static int spi_nor_clear_block_protection(struct spi_nor *nor)
>>> +{
>>> +       int ret;
>>> +       u8 sr, cr, sr_cr[2] = {0};
>>> +       u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
>>> +
>>> +       ret = read_cr(nor);
>>> +       dev_dbg(nor->dev, "CR = %08x\n", ret);
>>> +        if (ret < 0) {
>>> +                dev_err(nor->dev, "error while reading CR\n");
>>> +               return ret;
>>> +       }
>>> +       cr = ret;
>>> +
>>> +       if (cr & CR_QUAD_EN_SPAN) {
>>> +               /* disable quad if already set, must do it with 16-bit WRR 
>>> */
>>> +               ret = write_sr_cr(nor, sr_cr);
>>> +               if (ret) {
>>> +                       dev_err(nor->dev, "error diasbling quad mode\n");
>>
>> disabling
>>
>>> +                       return ret;
>>> +               }
>>
>> renesas_spi e6b10000.spi: DMA available
>> renesas_spi e6b10000.spi: registered master spi0
>> spi spi0.0: setup mode 3, 8 bits/w, 30000000 Hz max --> 0
>> m25p80 spi0.0: bfpt.dwords[1] = ffffffff
>> m25p80 spi0.0: bfpt.dwords[2] = ffffffff
>> m25p80 spi0.0: bfpt.dwords[3] = ffffffff
>> m25p80 spi0.0: bfpt.dwords[4] = ffffffff
>> m25p80 spi0.0: bfpt.dwords[5] = ffffffff
>> m25p80 spi0.0: bfpt.dwords[6] = ffffffff
>> m25p80 spi0.0: bfpt.dwords[7] = ffffffff
>> m25p80 spi0.0: bfpt.dwords[8] = ffffffff
>> m25p80 spi0.0: bfpt.dwords[9] = ffffffff
>> m25p80 spi0.0: bfpt.dwords[10] = 00000000
>> m25p80 spi0.0: bfpt.dwords[11] = 00000000
>> m25p80 spi0.0: bfpt.dwords[12] = 00000000
>> m25p80 spi0.0: bfpt.dwords[13] = 00000000
>> m25p80 spi0.0: bfpt.dwords[14] = 00000000
>> m25p80 spi0.0: bfpt.dwords[15] = 00000000
>> m25p80 spi0.0: bfpt.dwords[16] = 00000000
>> m25p80 spi0.0: failed to parse BFPT: err = -22
>> m25p80 spi0.0: spi_nor_init_params sfdp parse failed, ret =-22
>> m25p80 spi0.0: SR and CR before quad_enable:
>> m25p80 spi0.0: SR = 00000000
>> m25p80 spi0.0: CR = 00000002
>> m25p80 spi0.0: SR and CR after quad_enable:
>> m25p80 spi0.0: SR = 00000000
>> m25p80 spi0.0: CR = 00000002
>> m25p80 spi0.0: s25fl512s (65536 Kbytes)
>> m25p80 spi0.0: mtd .name = spi0.0, .size = 0x4000000 (64MiB),
>> .erasesize = 0x00040000 (256KiB) .numeraseregions = 0
>> 3 fixed-partitions partitions found on MTD device spi0.0
>> Creating 3 MTD partitions on "spi0.0":
>> 0x000000000000-0x000000080000 : "loader"
>> 0x000000080000-0x000000600000 : "user"
>> 0x000000600000-0x000004000000 : "flash"
>> renesas_spi e6b10000.spi: registered child spi0.0
>> renesas_spi e6b10000.spi: probed
>>
>> And /dev/mtd0 reading works fine.
>> Thanks!
>>
> 
> I'm glad that it worked, thanks for the help. I'll do a patch to fix this 
> case,
> but probably it will qualify for -next. Is -next ok for you?

I think this fix should be forwarded to v5.2-rc1 (or -rc2 at least) as
patch in question ("spi-nor: s25fl512s supports region locking") is part
of SPI NOR pull request for v5.2-rc1 and therefore would end up in
mainline v5.2-rc1 during the merge window.

-- 
Regards
Vignesh

Reply via email to