> +static inline u16
> _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
> {
> + return pci_irq_get_affinity_vector(ioc->pdev, raw_smp_processor_id());
> }
This looks extremely sketchy. Are we guaranteed to always have enough
MSI-X vectors that each CPU has it's own? I'd much prefer to keep the
indirection array of the existing code.
> +static int scsih_map_queues(struct Scsi_Host *shost)
> +{
> + struct MPT3SAS_ADAPTER *ioc = shost_priv(shost);
> +
> + return blk_mq_pci_map_queues(&shost->tag_set, ioc->pdev, 0);
> +}
Given that mpt3sas only supports a single hardware queue (and doesn't
set the nr_hw_queues field) this is pointless and won't have any effect.
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