On 12/02/2016 03:30 PM, Christoph Hellwig wrote:
+static inline u16 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc) { + return pci_irq_get_affinity_vector(ioc->pdev, raw_smp_processor_id()); }This looks extremely sketchy. Are we guaranteed to always have enough MSI-X vectors that each CPU has it's own? I'd much prefer to keep the indirection array of the existing code.
Hmm. Okay. will be doing so.
+static int scsih_map_queues(struct Scsi_Host *shost) +{ + struct MPT3SAS_ADAPTER *ioc = shost_priv(shost); + + return blk_mq_pci_map_queues(&shost->tag_set, ioc->pdev, 0); +}Given that mpt3sas only supports a single hardware queue (and doesn't set the nr_hw_queues field) this is pointless and won't have any effect.
Well, it does, actually. But this is part of another patchset enabling 'real' mq support. I'll be redoing the patch. Cheers, Hannes -- Dr. Hannes Reinecke Teamlead Storage & Networking [email protected] +49 911 74053 688 SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton HRB 21284 (AG Nürnberg) -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
