From: Ma Haijun <[email protected]> According to A10 user manual, the width of the drive configuration for each pin is only 2 bits. Fix the mask so we don't touch values for other pins.
Signed-off-by: Ma Haijun <[email protected]> Signed-off-by: Chen-Yu Tsau <[email protected]> --- arch/arm/cpu/armv7/sunxi/pinmux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c index 8428439..56671f6 100644 --- a/arch/arm/cpu/armv7/sunxi/pinmux.c +++ b/arch/arm/cpu/armv7/sunxi/pinmux.c @@ -69,7 +69,7 @@ int sunxi_gpio_set_drv(u32 pin, u32 val) &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; drv = readl(&pio->drv[0] + index); - drv &= ~(0xf << offset); + drv &= ~(0x3 << offset); drv |= val << offset; writel(drv, &pio->drv[0] + index); -- 1.8.5.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
