GMAC init code now exists in a glue layer driver under drivers/net,
instead of sunxi board initialization code. It has been cleaned up
to use macros for clock controls.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/cpu/armv7/sunxi/board.c | 32 +---------------------------
drivers/net/Makefile | 1 +
drivers/net/sunxi_gmac.c | 45 ++++++++++++++++++++++++++++++++++++++++
include/netdev.h | 1 +
4 files changed, 48 insertions(+), 31 deletions(-)
create mode 100644 drivers/net/sunxi_gmac.c
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 5d19a64..003570a 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -145,37 +145,7 @@ int cpu_eth_init(bd_t *bis)
#ifdef CONFIG_SUNXI_EMAC
sunxi_emac_initialize(bis);
#else
- int pin;
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* Set up clock gating */
- setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
-
- /* Set MII clock */
-#ifdef CONFIG_RGMII
- setbits_le32(&ccm->gmac_clk_cfg, (0x1 << 2) | (0x2 << 0));
-#else
- setbits_le32(&ccm->gmac_clk_cfg, 0);
-#endif
-
- /* Configure pin mux settings for GMAC */
- for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
-#ifdef CONFIG_RGMII
- /* skip unused pins in RGMII mode */
- if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
- continue;
-#endif
- sunxi_gpio_set_cfgpin(pin, 5);
- sunxi_gpio_set_drv(pin, 3);
- }
-
-#ifdef CONFIG_RGMII
- designware_initialize(0, SUNXI_GMAC_BASE, 0x1,
PHY_INTERFACE_MODE_RGMII);
-#else
- designware_initialize(0, SUNXI_GMAC_BASE, 0x1, PHY_INTERFACE_MODE_MII);
-#endif
-
+ sunxi_gmac_initialize(bis);
#endif
return 0;
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index d905fef..136479d 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_SH_ETHER) += sh_eth.o
obj-$(CONFIG_SMC91111) += smc91111.o
obj-$(CONFIG_SMC911X) += smc911x.o
obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
+obj-$(CONFIG_SUNXI_GMAC) += sunxi_gmac.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
diff --git a/drivers/net/sunxi_gmac.c b/drivers/net/sunxi_gmac.c
new file mode 100644
index 0000000..b8b9016
--- /dev/null
+++ b/drivers/net/sunxi_gmac.c
@@ -0,0 +1,45 @@
+#include <common.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+
+int sunxi_gmac_initialize(bd_t *bis)
+{
+ int pin;
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* Set up clock gating */
+ setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
+
+ /* Set MII clock */
+#ifdef CONFIG_RGMII
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+ CCM_GMAC_CTRL_GPIT_RGMII);
+#else
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+ CCM_GMAC_CTRL_GPIT_MII);
+#endif
+
+ /* Configure pin mux settings for GMAC */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
+ /* skip unused pins in RGMII mode */
+ if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
+ continue;
+#endif
+ sunxi_gpio_set_cfgpin(pin, 5);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+
+#ifdef CONFIG_RGMII
+ designware_initialize(0, SUNXI_GMAC_BASE, 0x1,
PHY_INTERFACE_MODE_RGMII);
+#else
+ designware_initialize(0, SUNXI_GMAC_BASE, 0x1, PHY_INTERFACE_MODE_MII);
+#endif
+
+ return 0;
+}
diff --git a/include/netdev.h b/include/netdev.h
index 16ee4ce..300664e 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -80,6 +80,7 @@ int skge_initialize(bd_t *bis);
int smc91111_initialize(u8 dev_num, int base_addr);
int smc911x_initialize(u8 dev_num, int base_addr);
int sunxi_emac_initialize(bd_t *bis);
+int sunxi_gmac_initialize(bd_t *bis);
int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
--
1.8.5.2
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