Signed-off-by: Ian Campbell <[email protected]>
---
arch/arm/cpu/armv7/sunxi/clock.c | 31 +++++++++++++++++++++++--------
arch/arm/include/asm/arch-sunxi/clock.h | 8 ++++++--
2 files changed, 29 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index f7eb37b..54d801c 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -21,12 +21,18 @@ static void clock_init_safe(void)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set safe defaults until PMU is configured */
- writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
- CPU_CLK_SRC_OSC24M << 16, &ccm->cpu_ahb_apb0_cfg);
+ writel(AXI_DIV_1 << AXI_DIV_SHIFT |
+ AHB_DIV_2 << AHB_DIV_SHIFT |
+ APB0_DIV_1 << APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_ahb_apb0_cfg);
writel(0xa1005000, &ccm->pll1_cfg);
sdelay(200);
- writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
- CPU_CLK_SRC_PLL1 << 16, &ccm->cpu_ahb_apb0_cfg);
+ writel(AXI_DIV_1 << AXI_DIV_SHIFT |
+ AHB_DIV_2 << AHB_DIV_SHIFT |
+ APB0_DIV_1 << APB0_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_ahb_apb0_cfg);
#ifdef CONFIG_SUN5I
/* Power on reset default for PLL6 is 2400 MHz, which is faster then
* it can reliable do :| Set it to a 600 MHz instead. */
@@ -158,12 +164,18 @@ void clock_set_pll1(int hz)
apb0 = apb0 - 1;
/* Switch to 24MHz clock while changing PLL1 */
- writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
- CPU_CLK_SRC_OSC24M << 16, &ccm->cpu_ahb_apb0_cfg);
+ writel(AXI_DIV_1 << AXI_DIV_SHIFT |
+ AHB_DIV_2 << AHB_DIV_SHIFT |
+ APB0_DIV_1 << APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_ahb_apb0_cfg);
sdelay(20);
/* Configure sys clock divisors */
- writel(axi << 0 | ahb << 4 | apb0 << 8 | CPU_CLK_SRC_OSC24M << 16,
+ writel(axi << AXI_DIV_SHIFT |
+ ahb << AHB_DIV_SHIFT |
+ apb0 << APB0_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
/* Configure PLL1 at the desired frequency */
@@ -171,7 +183,10 @@ void clock_set_pll1(int hz)
sdelay(200);
/* Switch CPU to PLL1 */
- writel(axi << 0 | ahb << 4 | apb0 << 8 | CPU_CLK_SRC_PLL1 << 16,
+ writel(axi << AXI_DIV_SHIFT |
+ ahb << AHB_DIV_SHIFT |
+ apb0 << APB0_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
sdelay(20);
}
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index 8ca2066..533f9b5 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -98,20 +98,24 @@ struct sunxi_ccm_reg {
#define APB1_FACTOR_N 0
/* clock divide */
-#define CPU_CLK_SRC_OSC24M 1
-#define CPU_CLK_SRC_PLL1 2
+#define AXI_DIV_SHIFT (0)
#define AXI_DIV_1 0
#define AXI_DIV_2 1
#define AXI_DIV_3 2
#define AXI_DIV_4 3
+#define AHB_DIV_SHIFT (4)
#define AHB_DIV_1 0
#define AHB_DIV_2 1
#define AHB_DIV_4 2
#define AHB_DIV_8 3
+#define APB0_DIV_SHIFT (8)
#define APB0_DIV_1 0
#define APB0_DIV_2 1
#define APB0_DIV_4 2
#define APB0_DIV_8 3
+#define CPU_CLK_SRC_SHIFT (16)
+#define CPU_CLK_SRC_OSC24M 1
+#define CPU_CLK_SRC_PLL1 2
#ifdef CONFIG_SUN5I
#define AHB_CLK_SRC_AXI 0
--
1.8.5.3
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