Hi, On Mon, Mar 17, 2014 at 08:28:26PM -0500, mrnuke wrote: > From c541c363b339d145f326747db5a3b0fabce2780a Mon Sep 17 00:00:00 2001 > From: Alexandru Gagniuc <[email protected]> > Date: Mon, 17 Mar 2014 20:08:05 -0500 > Subject: [PATCH] NOTFORMERGE: ARM: sun4i: spi: Allow transfers larger than > FIFO size > > SPI transfers were limited to one FIFO depth, which is 64 bytes. > This was an artificial limitation, however, as the hardware can handle > much larger bursts. To accommodate this, we enable the interrupt when > the Rx FIFO is 3/4 full, and drain the FIFO within the interrupt > handler. The 3/4 ratio was chosen arbitrarily, with the intention to > reduce the potential number of interrupts.
Cool. I started to work on this for the A31, but got nowhere since I couldn't figure out how to restart a transfer when the fifo was depleted. I assumed it wouldn't just work on the older SoCs too, but it seems like I was wrong :) > Since the SUN4I_CTL_TP bit is set, the hardware will pause > transmission whenever the FIFO is full, so there is no risk of losing > data if we can't service the interrupt in time. > > In the long term, we'll be better off handling this as DMA transfers, Yep. > but for now, this enables some userspace software, such as flashrom, > to use the A10 SPI controller via the spidev interfac without receing > -EINVAL. > > This patch should NOT be merged, as it only handles long Rx transfers. > Long Tx transfers have not been tested, and they will most likely fail > miserably. There is currently no refreshing of Tx FIFOs when they run > empty on long transfers. I'm not sure about what to do with this patch then :) Could you work on making it working for TX FIFOs too? Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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