From: Olliver Schinagl <[email protected]> This patch cleans up several macro's to remove magic values etc from clock.c and clock.h. Casualties being dragged in are some macro's from dram.c and the i2c driver.
Signed-off-by: Olliver Schinagl <[email protected]> --- arch/arm/cpu/armv7/sunxi/clock.c | 162 ++++++++------ arch/arm/cpu/armv7/sunxi/dram.c | 22 +- arch/arm/include/asm/arch-sunxi/clock.h | 370 ++++++++++++++++++++++---------- drivers/i2c/sunxi_i2c.c | 2 +- 4 files changed, 373 insertions(+), 183 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c index 980fb90..3472fc9 100644 --- a/arch/arm/cpu/armv7/sunxi/clock.c +++ b/arch/arm/cpu/armv7/sunxi/clock.c @@ -21,27 +21,38 @@ static void clock_init_safe(void) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Set safe defaults until PMU is configured */ - writel(AXI_DIV_1 << AXI_DIV_SHIFT | - AHB_DIV_2 << AHB_DIV_SHIFT | - APB0_DIV_1 << APB0_DIV_SHIFT | - CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + writel(CPU_AXI_CLK_DIV_RATIO(1) | + CPU_AHB_CLK_DIV_RATIO_2 | + CPU_APB0_CLK_DIV_RATIO_1 | + CPU_CLK_SRC_OSC24M, &ccm->cpu_ahb_apb0_cfg); - writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); + writel(CCM_PLL1_CFG_N(16) | + CCM_PLL1_CFG_LCK_TMR_CTRL(2) | + CCM_PLL1_CFG_BIAS_CUR(16) | + CCM_PLL1_CFG_VCO_BIAS(8) | + CCM_PLL1_CFG_EN, + &ccm->pll1_cfg); sdelay(200); - writel(AXI_DIV_1 << AXI_DIV_SHIFT | - AHB_DIV_2 << AHB_DIV_SHIFT | - APB0_DIV_1 << APB0_DIV_SHIFT | - CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + writel(CPU_AXI_CLK_DIV_RATIO(1) | + CPU_AHB_CLK_DIV_RATIO_2 | + CPU_APB0_CLK_DIV_RATIO_1 | + CPU_CLK_SRC_PLL1, &ccm->cpu_ahb_apb0_cfg); #ifdef CONFIG_SUN5I /* Power on reset default for PLL6 is 2400 MHz, which is faster then * it can reliable do :| Set it to a 600 MHz instead. */ - writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + writel(CCM_PLL6_CFG_M(1) | + CCM_PLL6_CFG_K(1) | + CCM_PLL6_CFG_N(25) | + CCM_PLL6_CFG_BW_WIDE | + CCM_PLL6_BIAS_CUR(16) | + CCM_PLL6_VCO_BIAS(16), + &ccm->pll6_cfg); #endif #ifdef CONFIG_SUN7I writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0), &ccm->ahb_gate0); - writel(0x1 << PLL6_ENABLE_OFFSET | readl(&ccm->pll6_cfg), + writel(CCM_PLL6_CFG_EN | readl(&ccm->pll6_cfg), &ccm->pll6_cfg); #endif } @@ -57,21 +68,33 @@ int clock_init(void) #endif /* uart clock source is apb1 */ - sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M); - sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N); - sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M); + clrsetbits_le32(&ccm->apb1_clk_div_cfg, + CCM_APB1_CLK_SRC_OSC24M, CCM_APB1_CLK_SRC_OSC24M); + clrsetbits_le32(&ccm->apb1_clk_div_cfg, + CCM_APB1_CLK_N_1, CCM_APB1_CLK_N_1); + clrsetbits_le32(&ccm->apb1_clk_div_cfg, + CCM_APB1_CLK_M(1), CCM_APB1_CLK_M(1)); /* open the clock for uart */ - sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN); + clrsetbits_le32(&ccm->apb1_clk_div_cfg, + CCM_APB_GATE_UART( + SUNXI_CONS_TO_UART(CONFIG_CONS_INDEX)), + CCM_APB_GATE_UART( + SUNXI_CONS_TO_UART(CONFIG_CONS_INDEX))); #ifdef CONFIG_NAND_SUNXI /* nand clock source is osc24m */ - sr32(&ccm->nand_sclk_cfg, 24, 2, NAND_CLK_SRC_OSC24); - sr32(&ccm->nand_sclk_cfg, 16, 2, NAND_CLK_DIV_N); - sr32(&ccm->nand_sclk_cfg, 0, 4, NAND_CLK_DIV_M); - sr32(&ccm->nand_sclk_cfg, 31, 1, CLK_GATE_OPEN); + clrsetbits_le32(&ccm->nand_sclk_cfg, + CCM_NAND_SCLK_SRC_OSC24M, CCM_NAND_SCLK_SRC_OSC24M); + clrsetbits_le32(&ccm->nand_sclk_cfg, + CCM_NAND_SCLK_N_1, CCM_NAND_SCLK_N_1); + clrsetbits_le32(&ccm->nand_sclk_cfg, + CCM_NAND_SCLK_M(1), CCM_NAND_SCLK_M(1)); + clrsetbits_le32(&ccm->nand_sclk_cfg, + CCM_NAND_SCLK_GATE_EN, CCM_NAND_SCLK_GATE_EN); /* open clock for nand */ - sr32(&ccm->ahb_gate0, AHB_GATE_OFFSET_NAND, 1, CLK_GATE_OPEN); + clrsetbits_le32(&ccm->nand_sclk_cfg, + CCM_AHB_GATE_NAND, CCM_AHB_GATE_NAND); #endif return 0; @@ -85,9 +108,10 @@ unsigned int clock_get_pll5(void) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; uint32_t rval = readl(&ccm->pll5_cfg); - int n = (rval >> 8) & 0x1f; - int k = ((rval >> 4) & 3) + 1; - int p = 1 << ((rval >> 16) & 3); + int n = CCM_PLL5_CFG_N_GET(rval); + int k = CCM_PLL5_CFG_K_GET(rval); + int p = CCM_PLL5_CFG_OUT_EXT_DIV_P_GET(rval); + return 24000000 * n * k / p; } @@ -96,40 +120,52 @@ int clock_twi_onoff(int port, int state) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (port > 2) + if (!(port & (CCM_APB_GATE_TWI1 | CCM_APB_GATE_TWI2 | + CCM_APB_GATE_TWI3 | CCM_APB_GATE_TWI4))) return -1; /* set the apb1 clock gate for twi */ - sr32(&ccm->apb1_gate, 0 + port, 1, state); + if (state) + clrsetbits_le32(&ccm->apb1_gate, CCM_APB_GATE_TWI(port), + CCM_APB_GATE_TWI(port)); + else + clrbits_le32(&ccm->apb1_gate, CCM_APB_GATE_TWI(port)); return 0; } #ifdef CONFIG_SPL_BUILD -#define PLL1_CFG(N, K, M, P) (1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | \ - 16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \ - (K) << 4 | 0 << 3 | 0 << 2 | (M) << 0) +/* PLL1 = (24MHz * N * K) / (M * P) */ +#define PLL1_CFG(N, K, M, P) (CCM_PLL1_CFG_M(M) | \ + CCM_PLL1_CFG_K(K) | \ + CCM_PLL1_CFG_N(N) | \ + CCM_PLL1_CFG_LCK_TMR_CTRL(2) | \ + CCM_PLL1_CFG_OUT_EXT_DIV_P(P) | \ + CCM_PLL1_CFG_BIAS_CUR(16) | \ + CCM_PLL1_CFG_VCO_BIAS(8) | \ + CCM_PLL1_CFG_EN) + #define RDIV(a, b) ((a + (b) - 1) / (b)) struct { u32 pll1_cfg; unsigned int freq; } pll1_para[] = { - { PLL1_CFG(16, 0, 0, 0), 384000000 }, - { PLL1_CFG(16, 1, 0, 0), 768000000 }, - { PLL1_CFG(20, 1, 0, 0), 960000000 }, - { PLL1_CFG(21, 1, 0, 0), 1008000000}, - { PLL1_CFG(22, 1, 0, 0), 1056000000}, - { PLL1_CFG(23, 1, 0, 0), 1104000000}, - { PLL1_CFG(24, 1, 0, 0), 1152000000}, - { PLL1_CFG(25, 1, 0, 0), 1200000000}, - { PLL1_CFG(26, 1, 0, 0), 1248000000}, - { PLL1_CFG(27, 1, 0, 0), 1296000000}, - { PLL1_CFG(28, 1, 0, 0), 1344000000}, - { PLL1_CFG(29, 1, 0, 0), 1392000000}, - { PLL1_CFG(30, 1, 0, 0), 1440000000}, - { PLL1_CFG(31, 1, 0, 0), 1488000000}, - { PLL1_CFG(31, 1, 0, 0), ~0}, + { PLL1_CFG(16, 1, 1, 1), 384000000 }, + { PLL1_CFG(16, 2, 1, 1), 768000000 }, + { PLL1_CFG(20, 2, 1, 1), 960000000 }, + { PLL1_CFG(21, 2, 1, 1), 1008000000}, + { PLL1_CFG(22, 2, 1, 1), 1056000000}, + { PLL1_CFG(23, 2, 1, 1), 1104000000}, + { PLL1_CFG(24, 2, 1, 1), 1152000000}, + { PLL1_CFG(25, 2, 1, 1), 1200000000}, + { PLL1_CFG(26, 2, 1, 1), 1248000000}, + { PLL1_CFG(27, 2, 1, 1), 1296000000}, + { PLL1_CFG(28, 2, 1, 1), 1344000000}, + { PLL1_CFG(29, 2, 1, 1), 1392000000}, + { PLL1_CFG(30, 2, 1, 1), 1440000000}, + { PLL1_CFG(31, 2, 1, 1), 1488000000}, + { PLL1_CFG(31, 2, 1, 1), ~0}, }; void clock_set_pll1(int hz) @@ -153,31 +189,36 @@ void clock_set_pll1(int hz) printf("CPU: %dHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); /* Map divisors to register values */ - axi = axi - 1; + axi = CPU_AXI_CLK_DIV_RATIO(axi); + if (ahb > 4) - ahb = 3; + ahb = CPU_AHB_CLK_DIV_RATIO_8; else if (ahb > 2) - ahb = 2; + ahb = CPU_AHB_CLK_DIV_RATIO_4; else if (ahb > 1) - ahb = 1; + ahb = CPU_AHB_CLK_DIV_RATIO_2; else - ahb = 0; - - apb0 = apb0 - 1; + ahb = CPU_AHB_CLK_DIV_RATIO_1; + + if (apb0 > 4) + apb0 = CPU_APB0_CLK_DIV_RATIO_8; + else if (apb0 > 2) + apb0 = CPU_APB0_CLK_DIV_RATIO_4; + else if (apb0 > 1) + apb0 = CPU_APB0_CLK_DIV_RATIO_2; + else + apb0 = CPU_APB0_CLK_DIV_RATIO_1; /* Switch to 24MHz clock while changing PLL1 */ - writel(AXI_DIV_1 << AXI_DIV_SHIFT | - AHB_DIV_2 << AHB_DIV_SHIFT | - APB0_DIV_1 << APB0_DIV_SHIFT | - CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + writel(CPU_AXI_CLK_DIV_RATIO(1) | + CPU_AHB_CLK_DIV_RATIO_2 | + CPU_APB0_CLK_DIV_RATIO_1 | + CPU_CLK_SRC_OSC24M, &ccm->cpu_ahb_apb0_cfg); sdelay(20); /* Configure sys clock divisors */ - writel(axi << AXI_DIV_SHIFT | - ahb << AHB_DIV_SHIFT | - apb0 << APB0_DIV_SHIFT | - CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + writel(axi | ahb | apb0 | CPU_CLK_SRC_OSC24M, &ccm->cpu_ahb_apb0_cfg); /* Configure PLL1 at the desired frequency */ @@ -185,10 +226,7 @@ void clock_set_pll1(int hz) sdelay(200); /* Switch CPU to PLL1 */ - writel(axi << AXI_DIV_SHIFT | - ahb << AHB_DIV_SHIFT | - apb0 << APB0_DIV_SHIFT | - CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + writel(axi | ahb | apb0 | CPU_CLK_SRC_PLL1, &ccm->cpu_ahb_apb0_cfg); sdelay(20); } diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c index 25251bb..d41443f 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -192,20 +192,20 @@ static void mctl_setup_dram_clock(u32 clk) /* setup DRAM PLL */ reg_val = readl(&ccm->pll5_cfg); - reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */ - reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); - reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */ - reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); - reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */ - reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); - reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */ - reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2)); - reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */ - reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */ + reg_val &= ~CCM_PLL5_CFG_M_MASK; /* set M to 0 (x1) */ + reg_val |= CCM_PLL5_CFG_M(2); /* set M to x2 */ + reg_val &= ~CCM_PLL5_CFG_K_MASK; /* set K to 0 (x1) */ + reg_val |= CCM_PLL5_CFG_K(2); /* set K to x2 */ + reg_val &= ~CCM_PLL5_CFG_N_MASK; /* set N to 0 (x0) */ + reg_val |= CCM_PLL5_CFG_N(clk / 24); /* set N to clk / 24 */ + reg_val &= ~CCM_PLL5_CFG_OUT_EXT_DIV_P_MASK; /* set P to 0 (x1) */ + reg_val |= CCM_PLL5_CFG_OUT_EXT_DIV_P_2; /* set P to x2 */ + reg_val &= ~CCM_PLL5_CFG_VCO_GAIN; /* PLL VCO Gain off */ + reg_val |= CCM_PLL5_CFG_EN; /* PLL On */ writel(reg_val, &ccm->pll5_cfg); udelay(5500); - setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); + setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CFG_DDR_CLK_EN); #if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I) /* reset GPS */ diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index b6184dc..9c08d84 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -33,7 +33,7 @@ struct sunxi_ccm_reg { u8 res3[0xc]; u32 pll_lock_dbg; /* 0x4c pll lock time debug */ u32 osc24m_cfg; /* 0x50 osc24m control */ - u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu, ahb and apb0 divide ratio */ u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ u32 axi_gate; /* 0x5c axi module clock gating */ u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ @@ -48,99 +48,276 @@ struct sunxi_ccm_reg { u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ u32 ts_clk_cfg; /* 0x98 transport stream clock control */ - u32 ss_clk_cfg; /* 0x9c */ - u32 spi0_clk_cfg; /* 0xa0 */ - u32 spi1_clk_cfg; /* 0xa4 */ - u32 spi2_clk_cfg; /* 0xa8 */ - u32 pata_clk_cfg; /* 0xac */ - u32 ir0_clk_cfg; /* 0xb0 */ - u32 ir1_clk_cfg; /* 0xb4 */ - u32 iis_clk_cfg; /* 0xb8 */ - u32 ac97_clk_cfg; /* 0xbc */ - u32 spdif_clk_cfg; /* 0xc0 */ - u32 keypad_clk_cfg; /* 0xc4 */ - u32 sata_clk_cfg; /* 0xc8 */ - u32 usb_clk_cfg; /* 0xcc */ - u32 gps_clk_cfg; /* 0xd0 */ - u32 spi3_clk_cfg; /* 0xd4 */ + u32 ss_clk_cfg; /* 0x9c security system clock control */ + u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ + u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ + u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */ + u32 pata_clk_cfg; /* 0xac parallel ATA clock control */ + u32 ir0_clk_cfg; /* 0xb0 infrared0 clock control */ + u32 ir1_clk_cfg; /* 0xb4 infrared1 clock control */ + u32 iis_clk_cfg; /* 0xb8 i2s clock control */ + u32 ac97_clk_cfg; /* 0xbc ac97 clock control */ + u32 spdif_clk_cfg; /* 0xc0 spdif clock control */ + u32 keypad_clk_cfg; /* 0xc4 keypad clock control */ + u32 sata_clk_cfg; /* 0xc8 serial ATA clock control */ + u32 usb_clk_cfg; /* 0xcc USB clock control */ + u32 gps_clk_cfg; /* 0xd0 GPS clock control */ + u32 spi3_clk_cfg; /* 0xd4 spi3 clock control */ u8 res5[0x28]; - u32 dram_clk_cfg; /* 0x100 */ - u32 be0_clk_cfg; /* 0x104 */ - u32 be1_clk_cfg; /* 0x108 */ - u32 fe0_clk_cfg; /* 0x10c */ - u32 fe1_clk_cfg; /* 0x110 */ - u32 mp_clk_cfg; /* 0x114 */ - u32 lcd0_ch0_clk_cfg; /* 0x118 */ - u32 lcd1_ch0_clk_cfg; /* 0x11c */ - u32 csi_isp_clk_cfg; /* 0x120 */ + u32 dram_clk_cfg; /* 0x100 DDR clock control */ + u32 be0_clk_cfg; /* 0x104 display backend0 clock control */ + u32 be1_clk_cfg; /* 0x108 display backend1 clock control */ + u32 fe0_clk_cfg; /* 0x10c display frontend0 clock control */ + u32 fe1_clk_cfg; /* 0x110 display frontend1 clock control */ + u32 mp_clk_cfg; /* 0x114 mixer processor clock control */ + u32 lcd0_ch0_clk_cfg; /* 0x118 lcd0 ch0 clock control */ + u32 lcd1_ch0_clk_cfg; /* 0x11c lcd1 ch0 clock control */ + u32 csi_isp_clk_cfg; /* 0x120 csi-isp clock contorl */ u8 res6[0x4]; - u32 tvd_clk_reg; /* 0x128 */ - u32 lcd0_ch1_clk_cfg; /* 0x12c */ - u32 lcd1_ch1_clk_cfg; /* 0x130 */ - u32 csi0_clk_cfg; /* 0x134 */ - u32 csi1_clk_cfg; /* 0x138 */ - u32 ve_clk_cfg; /* 0x13c */ - u32 audio_codec_clk_cfg; /* 0x140 */ - u32 avs_clk_cfg; /* 0x144 */ - u32 ace_clk_cfg; /* 0x148 */ - u32 lvds_clk_cfg; /* 0x14c */ - u32 hdmi_clk_cfg; /* 0x150 */ - u32 mali_clk_cfg; /* 0x154 */ + u32 tvd_clk_reg; /* 0x128 tv decoder clock control */ + u32 lcd0_ch1_clk_cfg; /* 0x12c lcd0 ch1 clock control */ + u32 lcd1_ch1_clk_cfg; /* 0x130 lcd1 ch1 clock control */ + u32 csi0_clk_cfg; /* 0x134 csi0 clock control */ + u32 csi1_clk_cfg; /* 0x138 csi1 clock control */ + u32 ve_clk_cfg; /* 0x13c video encoder clock control */ + u32 audio_codec_clk_cfg;/* 0x140 audio codec clock control */ + u32 avs_clk_cfg; /* 0x144 audio video sync clock control */ + u32 ace_clk_cfg; /* 0x148 audio codec encoder clock control */ + u32 lvds_clk_cfg; /* 0x14c lvcd clock control */ + u32 hdmi_clk_cfg; /* 0x150 hdmi clock control */ + u32 mali_clk_cfg; /* 0x154 mali clock control */ u8 res7[0x4]; - u32 mbus_clk_cfg; /* 0x15c */ + u32 mbus_clk_cfg; /* 0x15c memory bus clock control */ u8 res8[0x4]; - u32 gmac_clk_cfg; /* 0x164 */ + u32 gmac_clk_cfg; /* 0x164 gigabit mac clock control */ }; -/* apb1 bit field */ -#define APB1_CLK_SRC_OSC24M 0 -#define APB1_FACTOR_M 0 -#define APB1_FACTOR_N 0 - -/* clock divide */ -#define AXI_DIV_SHIFT (0) -#define AXI_DIV_1 0 -#define AXI_DIV_2 1 -#define AXI_DIV_3 2 -#define AXI_DIV_4 3 -#define AHB_DIV_SHIFT (4) -#define AHB_DIV_1 0 -#define AHB_DIV_2 1 -#define AHB_DIV_4 2 -#define AHB_DIV_8 3 -#define APB0_DIV_SHIFT (8) -#define APB0_DIV_1 0 -#define APB0_DIV_2 1 -#define APB0_DIV_4 2 -#define APB0_DIV_8 3 -#define CPU_CLK_SRC_SHIFT (16) -#define CPU_CLK_SRC_OSC24M 1 -#define CPU_CLK_SRC_PLL1 2 - -#define PLL1_CFG_DEFAULT 0xa1005000 +/* CPU_AHB_AP0_CFG */ +#define CPU_AXI_CLK_DIV_RATIO(n) ((((n) - 1) & 0x3) << 0) +#define CPU_ATB_APB_CLK_DIV_RATIO(n) ((((n) - 1) & 0x3) << 2) +#define CPU_AHB_CLK_DIV_RATIO(n) (((n) & 0x3) << 4) +#define __CPU_AHB_CLK_DIV_RATIO_1 0x0 +#define __CPU_AHB_CLK_DIV_RATIO_2 0x1 +#define __CPU_AHB_CLK_DIV_RATIO_4 0x2 +#define __CPU_AHB_CLK_DIV_RATIO_8 0x3 +#define CPU_AHB_CLK_DIV_RATIO_1 \ + CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_1) +#define CPU_AHB_CLK_DIV_RATIO_2 \ + CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_2) +#define CPU_AHB_CLK_DIV_RATIO_4 \ + CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_4) +#define CPU_AHB_CLK_DIV_RATIO_8 \ + CPU_AHB_CLK_DIV_RATIO(__CPU_AHB_CLK_DIV_RATIO_8) +#define CPU_AHB_CLK_SRC_AXI 0x0 +#define CPU_AHB_CLK_SRC_PLL62 0x1 +#define CPU_AHB_CLK_SRC_PLL6 0x2 +#define CPU_AHB_CLK_SRC(n) (((n) & 0x3) << 6) +#define CPU_APB0_CLK_DIV_RATIO(n) ((n) & 0x3 << 8) +#define __CPU_APB0_CLK_DIV_RATIO_1 0x0 +#define __CPU_APB0_CLK_DIV_RATIO_2 0x1 +#define __CPU_APB0_CLK_DIV_RATIO_4 0x2 +#define __CPU_APB0_CLK_DIV_RATIO_8 0x3 +#define CPU_APB0_CLK_DIV_RATIO_1 \ + CPU_APB0_CLK_DIV_RATIO(__CPU_APB0_CLK_DIV_RATIO_1) +#define CPU_APB0_CLK_DIV_RATIO_2 \ + CPU_APB0_CLK_DIV_RATIO(__CPU_APB0_CLK_DIV_RATIO_2) +#define CPU_APB0_CLK_DIV_RATIO_4 \ + CPU_APB0_CLK_DIV_RATIO(__CPU_APB0_CLK_DIV_RATIO_4) +#define CPU_APB0_CLK_DIV_RATIO_8 \ + CPU_APB0_CLK_DIV_RATIO(__CPU_APB0_CLK_DIV_RATIO_8) +#define __CPU_CLK_SRC_LOSC 0x0 +#define __CPU_CLK_SRC_OSC24M 0x1 +#define __CPU_CLK_SRC_PLL1 0x2 +#define __CPU_CLK_SRC_200MHZ_PLL6 0x3 +#define CPU_CLK_SRC(n) (((n) & 0x3) << 16) +#define CPU_CLK_SRC_LOSC \ + CPU_CLK_SRC(__CPU_CLK_SRC_LOSC) +#define CPU_CLK_SRC_OSC24M \ + CPU_CLK_SRC(__CPU_CLK_SRC_OSC24M) +#define CPU_CLK_SRC_PLL1 \ + CPU_CLK_SRC(__CPU_CLK_SRC_PLL1) +#define CPU_CLK_SRC_200MHZ_PLL6 \ + CPU_CLK_SRC(__CPU_CLK_SRC_200MHZ_PLL6) +/* CCM_PLL1_CFG */ +#define CCM_PLL1_CFG_M(n) ((((n) - 1) & 0x3) << 0) +#define CCM_PLL1_CFG_SIG_DELT_PAT_EN (0x1 << 2) +#define CCM_PLL1_CFG_SIG_DELT_PAT_IN (0x1 << 3) +#define CCM_PLL1_CFG_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_PLL1_CFG_N(n) (((n) & 0x1f) << 8) +#define CCM_PLL1_CFG_LCK_TMR_CTRL(n) (((n) & 0x7) << 13) +#define CCM_PLL1_CFG_OUT_EXT_DIV_P(n) (((n) & 0x3) << 16) +#define CCM_PLL1_CFG_OUT_EXT_DIV_P_GET(n) (0x1 << (((n) >> 16) & 0x3)) +#define __CCM_PLL1_CFG_OUT_EXT_DIV_P_1 0x0 +#define __CCM_PLL1_CFG_OUT_EXT_DIV_P_2 0x1 +#define __CCM_PLL1_CFG_OUT_EXT_DIV_P_4 0x2 +#define __CCM_PLL1_CFG_OUT_EXT_DIV_P_8 0x3 +#define CCM_PLL1_CFG_OUT_EXT_DIV_P_1 \ + CCM_PLL1_CFG_OUT_EXT_DIV_P(__CCM_PLL1_CFG_OUT_EXT_DIV_P_1) +#define CCM_PLL1_CFG_OUT_EXT_DIV_P_2 \ + CCM_PLL1_CFG_OUT_EXT_DIV_P(__CCM_PLL1_CFG_OUT_EXT_DIV_P_2) +#define CCM_PLL1_CFG_OUT_EXT_DIV_P_4 \ + CCM_PLL1_CFG_OUT_EXT_DIV_P(__CCM_PLL1_CFG_OUT_EXT_DIV_P_4) +#define CCM_PLL1_CFG_OUT_EXT_DIV_P_8 \ + CCM_PLL1_CFG_OUT_EXT_DIV_P(__CCM_PLL1_CFG_OUT_EXT_DIV_P_8) +#define CCM_PLL1_CFG_BIAS_CUR(n) (((n) & 0x1f) << 20) +#define CCM_PLL1_CFG_EX_PLL4 (0x1 << 25) +#define CCM_PLL1_CFG_VCO_BIAS(n) (((n) & 0xf) << 26) +#define CCM_PLL1_CFG_VCO_RST (0x1 << 30) +#define CCM_PLL1_CFG_EN (0x1 << 31) + +/* CCM_PLL5_CFG */ +#define CCM_PLL5_CFG_M(n) ((((n) - 1) & 0x3) << 0) +#define CCM_PLL5_CFG_M_MASK CCM_PLL5_CFG_M(0x4) +#define CCM_PLL5_CFG_M_GET(n) ((((n) >> 0) & 0x3) + 1) +#define CCM_PLL5_CFG_M1(n) (((n) & 0x3) << 2) +#define CCM_PLL5_CFG_M1_MASK CCM_PLL5_CFG_M1(0x4) +#define CCM_PLL5_CFG_M1_GET(n) (((n) >> 2) & 0x3) +#define CCM_PLL5_CFG_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_PLL5_CFG_K_MASK CCM_PLL5_CFG_K(0x4) +#define CCM_PLL5_CFG_K_GET(n) ((((n) >> 4) & 0x3) + 1) +#define CCM_PLL5_CFG_LDO_EN (0x1 << 7) +#define CCM_PLL5_CFG_N(n) (((n) & 0x1f) << 8) +#define CCM_PLL5_CFG_N_MASK CCM_PLL5_CFG_N(0x1f) +#define CCM_PLL5_CFG_N_GET(n) (((n) >> 8) & 0x1f) +#define CCM_PLL5_CFG_OUT_EXT_DIV_P(n) (((n) & 0x3) << 16) +#define CCM_PLL5_CFG_OUT_EXT_DIV_P_MASK CCM_PLL5_CFG_OUT_EXT_DIV_P(0x3) +#define CCM_PLL5_CFG_OUT_EXT_DIV_P_GET(n) (0x1 << (((n) >> 16) & 0x3)) +#define __CCM_PLL5_CFG_OUT_EXT_DIV_P_1 0x0 +#define __CCM_PLL5_CFG_OUT_EXT_DIV_P_2 0x1 +#define __CCM_PLL5_CFG_OUT_EXT_DIV_P_4 0x2 +#define __CCM_PLL5_CFG_OUT_EXT_DIV_P_8 0x3 +#define CCM_PLL5_CFG_OUT_EXT_DIV_P_1 \ + CCM_PLL5_CFG_OUT_EXT_DIV_P(__CCM_PLL5_CFG_OUT_EXT_DIV_P_1) +#define CCM_PLL5_CFG_OUT_EXT_DIV_P_2 \ + CCM_PLL5_CFG_OUT_EXT_DIV_P(__CCM_PLL5_CFG_OUT_EXT_DIV_P_2) +#define CCM_PLL5_CFG_OUT_EXT_DIV_P_4 \ + CCM_PLL5_CFG_OUT_EXT_DIV_P(__CCM_PLL5_CFG_OUT_EXT_DIV_P_4) +#define CCM_PLL5_CFG_OUT_EXT_DIV_P_8 \ + CCM_PLL5_CFG_OUT_EXT_DIV_P(__CCM_PLL5_CFG_OUT_EXT_DIV_P_8) +#define CCM_PLL5_CFG_BW_WIDE (0x1 << 18) +#define CCM_PLL5_CFG_VCO_GAIN (0x1 << 19) +#define CCM_PLL5_CFG_BIAS_CUR(n) ((((n) - 1) & 0x1f) << 20) +#define CCM_PLL5_CFG_BIAS_MASK CCM_PLL5_CFG_BIAS(0x20) +#define CCM_PLL5_CFG_VCO_BIAS(n) (((n) & 0xf ) << 25) +#define CCM_PLL5_CFG_DDR_CLK_EN (0x1 << 29) +#define CCM_PLL5_CFG_BYPASS (0x1 << 30) +#define CCM_PLL5_CFG_EN (0x1 << 31) + +/* CCM_PLL6_CFG */ +#define CCM_PLL6_CFG_M(n) ((((n) - 1) & 0x3) << 0) +#define CCM_PLL6_CFG_K(n) ((((n) - 1) & 0x3) << 4) +#define CCM_PLL6_CFG_DAMPING_CTRL(n) (((n) & 0x3) << 6) +#define CCM_PLL6_CFG_N(n) (((n) & 0x1f) << 8) +#define CCM_PLL6_CFG_SATA_CLK_EN (0x1 << 14) +#define CCM_PLL6_CFG_BW_WIDE (0x1 << 15) +#define CCM_PLL6_CFG_BIAS_CUR(n) (((n) & 0x1f) << 20) +#define CCM_PLL6_CFG_VCO_BIAS(n) (((n) & 0x1f) << 25) +#define CCM_PLL6_CFG_BYPASS (0x1 << 30) +#define CCM_PLL6_CFG_EN (0x1 << 31) + +/* CCM_APB1_CLK_DIV */ +#define CCM_APB1_CLK_M(n) ((((n) - 1) & 0x1f) << 0) +#define CCM_APB1_CLK_M_MASK CCM_APB1_CLK_M(0x20) +#define CCM_APB1_CLK_N(n) (((n) & 0x3) << 16) +#define CCM_APB1_CLK_N_MASK CCM_APB1_CLK_N(0x3) +#define CCM_APB1_CLK_N_GET(n) (0x1 << (((n) >> 16) & 0x3)) +#define __CCM_APB1_CLK_N_1 0x0 +#define __CCM_APB1_CLK_N_2 0x1 +#define __CCM_APB1_CLK_N_4 0x2 +#define __CCM_APB1_CLK_N_8 0x3 +#define CCM_APB1_CLK_N_1 \ + CCM_APB1_CLK_N(__CCM_APB1_CLK_N_1) +#define CCM_APB1_CLK_N_2 \ + CCM_APB1_CLK_N(__CCM_APB1_CLK_N_2) +#define CCM_APB1_CLK_N_4 \ + CCM_APB1_CLK_N(__CCM_APB1_CLK_N_4) +#define CCM_APB1_CLK_N_8 \ + CCM_APB1_CLK_N(__CCM_APB1_CLK_N_8) +#define CCM_APB1_CLK_SRC(n) (((n) & 0x3) << 24) +#define __CCM_APB1_CLK_SRC_OSC24M 0x0 +#define __CCM_APB1_CLK_SRC_PLL6 0x1 +#define __CCM_APB1_CLK_SRC_LOSC 0x2 +#define CCM_APB1_CLK_SRC_OSC24M \ + CCM_APB1_CLK_SRC(__CCM_APB1_CLK_SRC_OSC24M) +#define CCM_APB1_CLK_SRC_PLL6 \ + CCM_APB1_CLK_SRC(__CCM_APB1_CLK_SRC_PLL6) +#define CCM_APB1_CLK_SRC_LOSC \ + CCM_APB1_CLK_SRC(__CCM_APB1_CLK_SRC_LOSC) + +/* CCM_NAND_SCLK_CFG */ +#define CCM_NAND_SCLK_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_NAND_SCLK_M_MASK CCM_NAND_SCLK_M(0x10) +#define CCM_NAND_SCLK_N(n) (((n) & 0x3) << 16) +#define CCM_NAND_SCLK_N_MASK CCM_NAND_SCLK_N(0x3) +#define CCM_NAND_SCLK_N_GET(n) (0x1 << (((n) >> 16) & 0x3)) +#define __CCM_NAND_SCLK_N_1 0x0 +#define __CCM_NAND_SCLK_N_2 0x1 +#define __CCM_NAND_SCLK_N_4 0x2 +#define __CCM_NAND_SCLK_N_8 0x3 +#define CCM_NAND_SCLK_N_1 \ + CCM_NAND_SCLK_N(__CCM_NAND_SCLK_N_1) +#define CCM_NAND_SCLK_N_2 \ + CCM_NAND_SCLK_N(__CCM_NAND_SCLK_N_2) +#define CCM_NAND_SCLK_N_4 \ + CCM_NAND_SCLK_N(__CCM_NAND_SLK_N_4) +#define CCM_NAND_SCLK_N_8 \ + CCM_NAND_SCLK_N(__CCM_NAND_SCLK_N_8) +#define CCM_NAND_SCLK_SRC(n) (((n) & 0x3) << 24) +#define __CCM_NAND_SCLK_SRC_OSC24M 0x0 +#define __CCM_NAND_SCLK_SRC_PLL6 0x1 +#define __CCM_NAND_SCLK_SRC_LOSC 0x2 +#define CCM_NAND_SCLK_SRC_OSC24M \ + CCM_NAND_SCLK_SRC(__CCM_NAND_SCLK_SRC_OSC24M) +#define CCM_NAND_SCLK_SRC_PLL6 \ + CCM_NAND_SCLK_SRC(__CCM_NAND_SCLK_SRC_PLL6) +#define CCM_NAND_SCLK_SRC_LOSC \ + CCM_NAND_SCLK_SRC(__CCM_NAND_SCLK_SRC_LOSC) +#define CCM_NAND_SCLK_GATE_EN (0x1 << 31) + +/* CCM_APB1_GATE */ +/* todo: think of better names */ +#define CCM_APB_GATE_TWI0 0x1 +#define CCM_APB_GATE_TWI1 0x2 +#define CCM_APB_GATE_TWI2 0x4 +#define CCM_APB_GATE_TWI3 0x8 +#define CCM_APB_GATE_TWI4 0x8000 + +#define CCM_APB_GATE_PS20 0x1 +#define CCM_APB_GATE_PS21 0x2 + +#define CCM_APB_GATE_UART0 0x1 +#define CCM_APB_GATE_UART1 0x2 +#define CCM_APB_GATE_UART2 0x4 +#define CCM_APB_GATE_UART3 0x8 +#define CCM_APB_GATE_UART4 0x10 +#define CCM_APB_GATE_UART5 0x20 +#define CCM_APB_GATE_UART6 0x40 +#define CCM_APB_GATE_UART7 0x80 + +#ifdef CONFIG_SUN4I +#define CCM_APB_GATE_TWI4 0 +#endif #ifdef CONFIG_SUN5I -#define PLL6_CFG_DEFAULT 0x21009911 +#define CCM_APB_GATE_TWI3 0x0 +#define CCM_APB_GATE_TWI4 0x0 +#define CCM_APB_GATE_UART0 0x0 +#define CCM_APB_GATE_UART2 0x0 +#define CCM_APB_GATE_UART4 0x0 +#define CCM_APB_GATE_UART5 0x0 +#define CCM_APB_GATE_UART6 0x0 +#define CCM_APB_GATE_UART7 0x0 #endif #ifdef CONFIG_SUN7I -#define PLL6_ENABLE_OFFSET 31 #endif -#ifdef CONFIG_SUN5I -#define AHB_CLK_SRC_AXI 0 -#endif - -#define CLK_GATE_OPEN 0x1 -#define CLK_GATE_CLOSE 0x0 +#define SUNXI_CONS_TO_UART(n) (0x1 << (((n) - 1) & 0xff)) -/* nand clock */ -#define NAND_CLK_SRC_OSC24 0 -#define NAND_CLK_DIV_N 0 -#define NAND_CLK_DIV_M 0 - -/* gps clock */ -#define GPS_SCLK_GATING_OFF 0 -#define GPS_RESET 0 +#define CCM_APB_GATE_TWI(n) (((n) & 0x800f) << 0) +#define CCM_APB_GATE_CAN (0x1 << 4) +#define CCM_APB_GATE_SCR (0x1 << 5) +#define CCM_APB_GATE_PS2(n) (((n) & 0x3) << 6) +#define CCM_APB_GATE_UART(n) (((n) & 0xff) << 16) /* ahb clock gate bit offset */ #define AHB_GATE_OFFSET_GPS 26 @@ -174,35 +351,10 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_GMAC 17 #define CCM_AHB_GATE_GPS (0x1 << 26) -#define CCM_AHB_GATE_SDRAM (0x1 << 14) -#define CCM_AHB_GATE_DLL (0x1 << 15) #define CCM_AHB_GATE_ACE (0x1 << 16) - -#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) -#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3) -#define CCM_PLL5_CTRL_M_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2) -#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3) -#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) -#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3) -#define CCM_PLL5_CTRL_K_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_LDO (0x1 << 7) -#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8) -#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f) -#define CCM_PLL5_CTRL_N_X(n) (n) -#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16) -#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3) -#define CCM_PLL5_CTRL_P_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_BW (0x1 << 18) -#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19) -#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20) -#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f) -#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25) -#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29) -#define CCM_PLL5_CTRL_BYPASS (0x1 << 30) -#define CCM_PLL5_CTRL_EN (0x1 << 31) +#define CCM_AHB_GATE_DLL (0x1 << 15) +#define CCM_AHB_GATE_SDRAM (0x1 << 14) +#define CCM_AHB_GATE_NAND (0x1 << 13) #define CCM_GPS_CTRL_RESET (0x1 << 0) #define CCM_GPS_CTRL_GATE (0x1 << 1) diff --git a/drivers/i2c/sunxi_i2c.c b/drivers/i2c/sunxi_i2c.c index 5fe790a..b9bcf63 100644 --- a/drivers/i2c/sunxi_i2c.c +++ b/drivers/i2c/sunxi_i2c.c @@ -21,7 +21,7 @@ void i2c_init(int speed, int slaveaddr) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), 2); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), 2); - clock_twi_onoff(0, 1); + clock_twi_onoff(CCM_APB_GATE_TWI0, 1); /* Enable the i2c bus */ writel(TWI_CTL_BUSEN, &i2c_base->ctl); -- 1.8.3.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. 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