Hi Dmitry, Stefan,
On 06/05/2014 23:14, Dmitriy B. wrote: > 2014-05-06 21:08 GMT+04:00 Stefan Monnier <[email protected] > <mailto:[email protected]>>: > > I remember discussion of an MTD driver for sunxi a while back. > I can't find it in sunxi-devel, tho. Is it only available for > sunxi-3.4, or is there a branch for this MTD driver that works on > newer > (DT-based) kernels? > > > Boris Brezillon developed such driver from the sources of 3.4 one. I > added him to cc. He tested it on Cubietruck board. > > You can check it out > there http://lists.infradead.org/pipermail/linux-mtd/2014-March/052550.html > and as cc to our mailing list (use search). > > I think driver got stuck before mainline because of the trouble of > getting needed MTD framework changes pushed/tested. A quick update on the driver status: * From a technical POV the driver is working on the cubietruck board (A20 based board). When I say it works, it means it supports all the functionnality needed to access the NAND flash: - HW ECC - HW randomizer - read retry on the hynix NAND - boot0 and boot1 partition support (per partition ECC and randomizer config) This driver might need some improvements (mostly performance improvements): - dma support - better randomizer handling - ... Now, if you want to port this to another board using an A20 SoC, you'll have to check for this: - does your NAND chip require read retry, and if it does, is read retry for this NAND chip supported in the mainline kernel. If it's not you'll have to implement it. - check your NAND chip timings and ECC requirements and define your NAND chip DT node accordingly - check which CS your NAND chip is connected on, and again, define your NAND chip accordingly (not that your board might have several NAND connected, though I haven't seen such designs in the wild). If you want to port this driver to another SoC, you should do pretty much the same (I started to port it to the A10 with mrnuke's and wigyori's help, but didn't have time to finish) However, on other SoCs (at least it is the case for the A10) you might not be able to read/write boot0/boot1 partitions because they might use a fixed layout (1024 bytes data + X bytes of ECC per pages not matter the page size, I don't remember the value for X :-)) instead of using the standard NAND layout (depends on the NAND chip you're using). I still haven't found any good solution to handle this problem. * About the mainlining process: I discussed it with the MTD maintainer (Brian Norris) during ELC, and this won't be easy (or at least quick) to get all these modification merged. I think we can have base support for the NAND controller as a first step (see https://lkml.org/lkml/2014/3/12/435). By base support I mean: - HW/SW ECC - NAND controller with up 8 NAND chips This base support won't include: - HW randomizer - boot0/boot1 parititions (because they requires per partition ECC/randomizer config) because this requires modifying the NAND core code, which takes more time to review and test. That's all for the moment. I'll keep you informed of my progress (if any). Best Regards, Boris > > Best Regards, > Dmitriy Beykun > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
