Hi all,
I am trying to overclock the A31 higher than 1008MHz and I am getting
deterioration in performance.
The way I work is execute a small program from u-boot which redefines the N
multiplayer of PLL1 and then runs some CPU-intentive routine (to measure
performance).
Here are the results I get (the N multiplier is given in the small brackets
starting from 18):
CPU Freq = 864Mhz (18)
run in 10Hz, 94ms
PLL1 is ENABLED P:2 M:1 K:3 N:18 Sigma:0 Lock:0 Freq:432Mhz coreclk:864Mhz
CPU Freq = 912Mhz (19)
run in 11Hz, 89ms
PLL1 is ENABLED P:2 M:1 K:3 N:19 Sigma:0 Lock:0 Freq:456Mhz coreclk:912Mhz
CPU Freq = 960Mhz (20)
run in 11Hz, 85ms
PLL1 is ENABLED P:2 M:1 K:3 N:20 Sigma:0 Lock:0 Freq:480Mhz coreclk:960Mhz
CPU Freq = 1008Mhz (21)
run in 12Hz, 81ms
PLL1 is ENABLED P:2 M:1 K:3 N:21 Sigma:0 Lock:0 Freq:504Mhz coreclk:1008Mhz
CPU Freq = 1056Mhz (22)
run in 12Hz, 77ms
PLL1 is ENABLED P:2 M:1 K:3 N:22 Sigma:0 Lock:0 Freq:528Mhz coreclk:1056Mhz
CPU Freq = 1104Mhz (23)
run in 9Hz, 101ms
PLL1 is ENABLED P:2 M:1 K:3 N:23 Sigma:0 Lock:0 Freq:552Mhz coreclk:1104Mhz
CPU Freq = 1152Mhz (24)
run in 9Hz, 101ms
PLL1 is ENABLED P:2 M:1 K:3 N:24 Sigma:0 Lock:0 Freq:576Mhz coreclk:1152Mhz
CPU Freq = 1200Mhz (25)
run in 9Hz, 101ms
PLL1 is ENABLED P:2 M:1 K:3 N:25 Sigma:0 Lock:0 Freq:600Mhz coreclk:1200Mhz
CPU Freq = 1248Mhz (26)
run in 9Hz, 101ms
PLL1 is ENABLED P:2 M:1 K:3 N:26 Sigma:0 Lock:0 Freq:624Mhz coreclk:1248Mhz
CPU Freq = 1296Mhz (27)
run in 9Hz, 101ms
PLL1 is ENABLED P:2 M:1 K:3 N:27 Sigma:0 Lock:0 Freq:648Mhz coreclk:1296Mhz
CPU Freq = 1344Mhz (28)
run in 9Hz, 101ms
PLL1 is ENABLED P:2 M:1 K:3 N:28 Sigma:0 Lock:0 Freq:672Mhz coreclk:1344Mhz
CPU Freq = 1392Mhz (29)
run in 9Hz, 101ms
PLL1 is ENABLED P:2 M:1 K:3 N:29 Sigma:0 Lock:0 Freq:696Mhz coreclk:1392Mhz
As you can see, after 1008 (or 1056) there's a _decrease_ in performance.
Does anyone knows how higher performance can be achieved?
I should note that the PRCM PLL1 control register is set to 3.3v (rather
than 2.5v) and the leo to 1.45v. Both numbers are the maximal voltages
possible.
Thank!
---------------------
typedef struct __CCMU_PLL_CTL1
{
__u32 LdoEn:1; //bit0, ldo enable, 0:disable, 1:enable
__u32 Ldo1En:1; //bit1, ldo1 enable, 0:disable, 1:enable
__u32 CrystalEn:1; //bit2, crystal enable, 0:disable, 1:enable
__u32 ClkTstEn:1; //bit3, clock test enable, 0:disable,
1:enable
__u32 reserved1:11; //bit4, reserved
__u32 PllPwr:1; //bit15, pll input power select, 0:2.5v,
1:3.3v
__u32 PllVdd:3; //bit16, pll vdd ldo output,
000~111:1.10v~1.45v, 0.05v per-step
__u32 reserved2:5; //bit19, reserved
__u32 KeyFiled:8; //bit24, key filed for ldo enable bit,
should be 0xA7
} __ccmu_pll_ctl1_t;
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