On Mon, 13 Oct 2014 13:10:28 +0200
Hans de Goede <[email protected]> wrote:

> Hi,
> 
> On 10/04/2014 07:53 AM, Siarhei Siamashka wrote:
> > When PLL5P is used as a parent clock for some of the peripherals,
> > the current code just selects some hardcoded divisors. This happens
> > to work, but only under assumption that the PLL5P clock speed is
> > somewhere between 360MHz and 480MHz (the typical DRAM clock speeds).
> > 
> > However with some tweaks for the DRAM parameters, it is possible to
> > clock DRAM up to 600MHz and more on some devices:
> > 
> >     http://lists.denx.de/pipermail/u-boot/2014-July/183981.html
> > 
> > And this introduces concerns about the hardcoded divisors in the
> > kernel, which may cause some peripherals to operate at abnormally
> > high clock speeds if the PLL5 clock speed is too fast (PLL5 is used
> > for clocking DRAM).
> > 
> > Moreover, it makes sense to avoid pre-dividing PLL5P and make it run
> > even faster than DRAM. This provides better granularity of the clock
> > speed selection for MBUS, G2D and everything else that is using PLL5P
> > as the parent clock. but running PLL5P faster means that the hardcoded
> > divisors become even more inappropriate.
> > 
> > This patch improves the clock divisors selection for G2D, ACE and
> > DEBE to insure that they can work correctly with any PLL5P clock
> > speed.
> > 
> > Signed-off-by: Siarhei Siamashka <[email protected]>
> 
> Looks good:
> 
> Acked-by: Hans de Goede <[email protected]>
> 
> Can we please get this merged,

You know the rules. Every patch needs to be approved by at least one
person other than the submitter.

Thanks for the review. Pushed to stage/sunxi-3.4

> I'm working on getting the sunxi-3.4 kernels to work with upstream
> u-boot, so that we can stop maintaining our own fork,
> and this is necessary for this.

I hope we don't get in each other's way with this stuff.

-- 
Best regards,
Siarhei Siamashka

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