Hi,

On Wed, Dec 03, 2014 at 02:35:57PM +0800, Chen-Yu Tsai wrote:
> The mmc module clocks are A80 specific module 0 (storage) type clocks.
> 
> Signed-off-by: Chen-Yu Tsai <[email protected]>
> Signed-off-by: Andreas Färber <[email protected]>
> ---
>  arch/arm/boot/dts/sun9i-a80.dtsi | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi 
> b/arch/arm/boot/dts/sun9i-a80.dtsi
> index 494714f..33d18dc 100644
> --- a/arch/arm/boot/dts/sun9i-a80.dtsi
> +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
> @@ -215,6 +215,38 @@
>                       clock-output-names = "cci400";
>               };
>  
> +             mmc0_clk: clk@06000410 {
> +                     #clock-cells = <0>;
> +                     compatible = "allwinner,sun9i-a80-mod0-clk";
> +                     reg = <0x06000410 0x4>;
> +                     clocks = <&osc24M>, <&pll4>;
> +                     clock-output-names = "mmc0";
> +             };
> +
> +             mmc1_clk: clk@06000414 {
> +                     #clock-cells = <0>;
> +                     compatible = "allwinner,sun9i-a80-mod0-clk";
> +                     reg = <0x06000414 0x4>;
> +                     clocks = <&osc24M>, <&pll4>;
> +                     clock-output-names = "mmc1";
> +             };
> +
> +             mmc2_clk: clk@06000418 {
> +                     #clock-cells = <0>;
> +                     compatible = "allwinner,sun9i-a80-mod0-clk";
> +                     reg = <0x06000418 0x4>;
> +                     clocks = <&osc24M>, <&pll4>;
> +                     clock-output-names = "mmc2";
> +             };
> +
> +             mmc3_clk: clk@0600041c {
> +                     #clock-cells = <0>;
> +                     compatible = "allwinner,sun9i-a80-mod0-clk";
> +                     reg = <0x0600041c 0x4>;
> +                     clocks = <&osc24M>, <&pll4>;
> +                     clock-output-names = "mmc3";
> +             };
> +

How is the phase stuff supposed to work? Is this still used on the A80?

Also, wasn't the mux supposed to have 4 bits (so something like at
least 9 parent clocks?) given your previous patch?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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