On Wed, 2015-02-18 at 22:29 -0800, TsvetanUsunov wrote: > Hi > > For A13-OLinuxino till now we conservatively used the Linux-Sunxi > uboot, but we recently got new lot of Samsung memories and we > decided to tweak some parameters for this DDR in Linux-Sunxi uboot > and found problems. > As this uboot is with status not maintained anymore I will not > discuss the problems, as probably no one will spend time on it, so > we wisely decided to move to mainline uboot :) but it seems there > are other issues to address. > > The PLL5 and PLL6 values are changed and this cause problems, this > is what we found so far:
What version (release or git commit-id) was the mainline u-boot? PS. ssvb has done lots of work so far documenting the various memory chips used on sunxi hardware: http://linux-sunxi.org/DDR3 And although it's not really related to A13, we still lack the source code for 'libdram' for newer chips (submitted as binary files in the u- boot code drop by Allwinner and subsequently removed after we asked for the source code): https://github.com/allwinner-zh/bootloader/issues/1 > > 1. mainline u-boot > ================= > > 1.1 pll5 > address 0x01c20020, value 0xb1049091 - P=1, N=16, K=2, M=2. > > The PLL5 output for DDR = (24MHz*N*K)/M. DDR=24*16*2/2 = > 384MHz > The PLL5 output for other module = (24MHz*N*K)/P. > DDR=24*16*2/1 = 768MHz - This high frequency cause LCDs connected > to the board to flicker > > 1.2 pll6 > address 0x01c20028, value 0xA1009900 - N=25, K=1, M=1 > > The PLL6 output is (24MHz*N*K)/M/2 = 24*25*1/1/2 = 300MHz > > 1.3 MBUS clock > address 0x01c2015c, value 0x81000001 - MBUS clock source is > PLL6/2 = 300/2 = 150MHz - This is connected to PLL6 setup, at this > 150 Mhz the board cant play video smoothly and sometimes drop video > packets when the video is playing > > > 2. sunxi u-boot > ================= > > 1.1 pll5 > address 0x01c20020, value 0xb1049091 - P=2, N=17, K=2, M=2. > > The PLL5 output for DDR = (24MHz*N*K)/M. DDR=24*17*2/2 = > 408MHz > The PLL5 output for other module = (24MHz*N*K)/P. > DDR=24*16*2/2 = 408MHz - this frequency was OK, There is no problem > with LCD flickering, why the frequency increase was necessary? > > 1.2 pll6 > address 0x01c20028, value 0xA1009900 - N=25, K=1, M=1 > > The PLL6 output is (24MHz*N*K)/M/2 = 24*25*1/1/2 = 300MHz > > 1.3 about MBUS clock > address 0x01c2015c, value 0x82000001 - MBUS clock source is > PLL5/2 = 408/2 = 204MHz - at this frequency No packet drop when the > video is playing > > > Can you tell me the reasons for the PLL5 and PLL6 frequency changes > to mainline uboot? > > Best regards > Tsvetan > -- > You received this message because you are subscribed to the Google > Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, > send an email to [email protected]. > For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
