On Sat, Oct 3, 2015 at 12:32 PM, Rock Slate <rockslat...@gmail.com> wrote:
> Hi, > > Thanks for the reply. Both yes and no. The A13 comes in a nice friendly > package which is easy to solder. However the FBGA on the DDR3 is really a > nightmare. If not placed correctly, I would have to reball the chip and > this is a little tough to do since I am not sure if I have the right > experience for achieving this. > > However , I have some dedicated code which is really small(something like > toggling a few pins) to control another interface which I would like to do > even if the DDR does not work(signal integrity is also a problem , even if > ODT is present). I dont want to put in another MCU just for this purpose. > > I was wondering if its possible to run the A13 without the DDRAM being > configured. Although I havent read the cortex A8 manual , I am assuming > that UBOOT at some level should be able to achieve what I want. > > It is also an interesting topic since I dont find many papers detailing > how to use the ARM without external RAM apart from > http://www.coreboot.org/images/6/6c/LBCar.pdf so that I can use it as a > microcontroller in the initial stages of development. > > > On Sat, Oct 3, 2015 at 11:30 AM, Siarhei Siamashka < > siarhei.siamas...@gmail.com> wrote: > >> On Sat, 3 Oct 2015 09:23:35 +0530 >> Rock Slate <rockslat...@gmail.com> wrote: >> >> > Hi, >> > >> > In general I know the x86 architecture BIOS will refuse to boot if valid >> > ram space is not found. On linux I can use the BadRam kernel patches to >> > ignore bad areas of memory. However just out of curiosity, I am >> wondering >> > whether using the internal cache would be sufficient to run small >> programs >> > to access GPIOS. Right now I am not talking about booting Linux. I want >> to >> > know if I can run some really small RTOS on A13 without RAM? >> >> Hi, >> >> The A13 SoC has 48KiB of SRAM, which is used to run the initial part >> of the bootloader. The DRAM is even not initialized at this step. >> >> This initial part of the bootloader is loaded by the BROM from the SD >> card, NAND or other standard locations. But it needs to have a special >> magic signature and a valid checksum. Also there is a size limitation >> for it (something between 24KiB and 32KiB). >> >> You can check the http://linux-sunxi.org/BROM page for a brief >> description of the boot sequence. And also the A13 user manual >> for the rest of the information. >> >> For bare-metal programming experiments, you can also try to use >> FEL mode and upload & execute snippets of code over USB. So that >> you don't need inserting and removing SD cards all the time. >> >> Regarding the use of the L2 cache (256KiB) for additional data storage, >> this may be an interesting research topic. I can't say offhand whether >> it can be really configured this way and used safely. >> >> Are you planning to design an A13 board without DDR3, tailored for >> some special purpose? >> >> -- >> Best regards, >> Siarhei Siamashka >> > > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
