Hi Jon,

On Monday, October 5, 2015 at 12:19:50 AM UTC+2, Jon Smirl wrote:
>
> On Sun, Oct 4, 2015 at 6:14 PM, [email protected] <javascript:> <
> [email protected] <javascript:>> wrote: 
> > On Sun, Oct 4, 2015 at 4:26 AM, Alexis Jeandet <[email protected] 
> <javascript:>> wrote: 
> >> 
> >> Hi, 
> >> On Saturday, October 3, 2015 at 1:39:55 PM UTC+2, Jon Smirl wrote: 
> >>> 
> >>> On Sat, Oct 3, 2015 at 3:53 AM, Rock Slate <[email protected]> 
> wrote: 
> >>> > Wow, that's a really detailed response. Thanks a lot for the 
> pointers. I 
> >>> > will definitely look into this and will let you know as I proceed. 
> >>> 
> >>> On other processors I have seen people attach SRAM to the LCD 
> >>> interface. That technique may be possible on Allwinner but it will 
> >>> need some investigation. 
> >>> 
> >>  I've seen the opposite, I'm interested if you have some links, it 
> would be 
> >> a good point to link FPGA to allwinner devices. 
> > 
> > I believe it works by putting the LCD controller into 8080 mode, then 
> > the LCD interface looks like an ISA bus. Normal SRAM has no problem 
> > attaching to the ISA bus. But I don't know if the Allwinner LCD 
> > controller supports 8080 mode on LCD panels. 
> > 
>
> The A10 says it supports 8080 mode for LCD panels. The display 
> controller section is missing from the A13 manual. 
>
>
In my understanding, the 8080 mode with LCD just uses a data bus and a 
CMD/DATA bit but no address bus. When we connect LCD to a memory controller 
in 8080 mode we connect the CMD/DATA bit to an address bit in order to 
automatically switch between DATA and CMD. It also allow to copy pixel 
buffers directly from RAM to LCD GRAM with DMA.

In this case I don't understand how to handle the SRAM address bus without 
additional logic. I should have missed something.
 
Alexis.

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