Hi,
On 22/02/16 15:45, LABBE Corentin wrote:
> The sun8i-emac is an ethernet MAC hardware that support 10/100/1000
> speed. TODO
>
> This patch enable the sun8i-emac on the Allwinner A20 SoC Device-tree.
>
> Signed-off-by: LABBE Corentin <clabbe.montj...@gmail.com>
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 0faa38a..b1d949f 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -500,6 +500,17 @@
> allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> };
> +
> + emac_pins_a: emac0@0 {
> + allwinner,pins = "PD0", "PD1", "PD2", "PD3",
> + "PD4", "PD5", "PD6", "PD7",
> + "PD8", "PD9", "PD10", "PD11",
> + "PD12", "PD13", "PD14", "PD15",
> + "PD16", "PD17";
> + allwinner,function = "emac";
> + allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> };
>
> bus_rst: reset@01c202c0 {
> @@ -574,6 +585,16 @@
> status = "disabled";
> };
>
> + emac: ethernet@1c30000 {
> + compatible = "allwinner,sun8i-h3-emac";
> + reg = <0x01c30000 0x1054>;
Why is this region so big here? Looking at the code the highest register
offset is less than 0x100, so I suggest you go with that here (or use
0x1000 to cover a whole page).
Or did I miss some offsetting in the driver?
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&bus_rst 17>, <&bus_rst 66>;
> + reset-names = "ahb", "ephy";
> + clocks = <&bus_gates 17>, <&bus_gates 128>;
> + clock-names = "ahb2_gmac", "ahb1_ephy";
> + };
Also you need to describe the binding here, possibly mentioning that
ephy and ahb1_ephy are optional if the SoC has an internal PHY.
Cheers,
Andre.
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