>This allows the SRAM section A2 to be exclusively used by >the OpenRISC core. > >There are no substantial differences between H3 and A10/A13/A20. >It just has 64 KiB of SRAM starting at the address 0x0 instead >of 48 KiB. > >Signed-off-by: Siarhei Siamashka <siarhei.siamas...@gmail.com> >---
Does this mean that the MMU translation table will limit the SPL size to 32K? If so, it might be worth to add a corresponding note.
Given that the H3 has 64K SRAM available, what about the area 0xC000 to 0xFFFF? Would setting mmu_tt_addr to 0xC000 be feasible, bringing the H3 even closer to A20, in terms of memory layout below that address and maximum SPL size?
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