Em segunda-feira, 13 de fevereiro de 2017 09:52:53 UTC-3, Mark Brown escreveu: > > This should be controlled by the SPI mode settings, different chips have > different requirements. If the controller supports multiple modes then > it should expose that and let the drivers and system integrations > choose. > Do you mean SPI_CPHA/SPI_CPOL, right? Well, I don't know how this mode can to fit in existing modes. Since this bit is to control when the data will be sampled, in the same clock edge or at the edge that is half cycle delayed. That has nothing to do with SPI_CPHA/SPI_CPOL.
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