Em quinta-feira, 2 de março de 2017 17:44:16 UTC-3, Siarhei Siamashka escreveu:
> Here is a short summary. Older Allwinner A10/A13 SoCs used to have > reserved RAZ/WI (Read-As-Zero, Writes Ignored) bits 20-31 in the > SPI_CTL register. Newer Allwinner A20 SoC introduced some sort of > a wacky half-cycle delay mode and used the previously reserved bit > 20 from the SPI_CTL to enable/disable it. Now the tricky part is that > the meaning of this new bit is inverted for some unknown reason: the > wacky mode is activated when the bit is set to zero, while the standard > behaviour (same as A10/A13) is preserved when this bit is set to 1. The > reset default of this bit is 1 on A20 (normal SPI behaviour). The > problem of the current SPI driver is that it clears bits 20-31 of > SPI_CTL, which results in normal SPI behaviour on A10/A13, and a wacky > half-cycle delayed mode on A20. Your bugfix just makes A20 behave in > the same way as A10/A13. These are the exact words I was looking for, thanks Siarhei. And I don't really know which chip could to use this wacky half-cycle delay mode. Anyway, maybe a new dts property could be a solution to let user to enable or not normal mode and half-cycle mode? Best regards, Vinicius -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
