On Mon, Nov 5, 2018 at 3:49 PM Jagan Teki <[email protected]> wrote: > > MUX bits for MMC clock register range are 25:24 where 24 is shift > and 2 is width So fix the width number from 3 to 2. > > Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]> However, given that most of the other module clocks have bits 26:24 as their mux bits, and the mmc clocks use 3 bits to denote the values and corresponding clock parents, I would have appreciated you actually doing tests to confirm which of these errors is the actual error, and not just say "the user manual says so", because it is not always completely correct. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
