On Thu, Dec 31, 2020 at 03:29:42PM +0100, Paul Kocialkowski wrote: > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge > found on Allwinner SoCs such as the A31 and V3/V3s. > > It is a standalone block, connected to the CSI controller on one side > and to the MIPI D-PHY block on the other. It has a dedicated address > space, interrupt line and clock. > > It is represented as a V4L2 subdev to the CSI controller and takes a > MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and > media controller API. > > Only 8-bit and 10-bit Bayer formats are currently supported. > While up to 4 internal channels to the CSI controller exist, only one > is currently supported by this implementation. > > Signed-off-by: Paul Kocialkowski <[email protected]>
CHECK: Alignment should match open parenthesis :) Once fixed, Acked-by: Maxime Ripard <[email protected]> Maxime -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210108095419.quegerk52wwhrxye%40gilmour.
signature.asc
Description: PGP signature
