Hi Dave, > Added that patch and moved my <&ccu CLK_EMAC_25M> into the mdio/phy DT > section. > > Manually setting EMAC_25M_CLK_REG does work and produces a nice 25Mhz > sine wave clock output on the pin, however the driver isn't doing this > (even with that patch). The driver does release phy reset during > init, but not enable the 25mhz clock output.
Is it actually a sine wave on your board? I get a square wave here... had to use a ground spring rather than the alligator clip though; otherwise the waveform was nasty-looking. I was using PE10, not PG11, because PG11 is already in use on the Lichee RV 86 Panel. > If I manually (outside of the driver) release the phy reset GPIO and > enable the 25mhz output, the phy comes online and starts generating a > 50mhz clock back towards the MAC on the RMII-TXCK pin. > > I verified clocks going in both directions with a scope and once the > TXCK clock makes it back to the EMAC from the PHY it looks like it > will exit soft-reset. > > So at this point, getting the ephy-25mhz enabled by mac and/or mdio > drivers should fix things. > > I placed these in both the mdiobus and phy clauses of the DTS but it's > not getting picked up: > > clocks = <&ccu CLK_EMAC_25M>; > clock-names = "ephy25m"; > OK, I need to try it out to see if I can find the problem. Maybe someone more experienced than me can weight in in the meantime, though. Matt -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/3542467.iIbC2pHGDl%40mt-dell-tumbleweed.
