On 02/14/2013 03:01 AM, Peter De Schrijver wrote: > On Wed, Feb 13, 2013 at 05:48:03PM +0100, Stephen Warren wrote: ... >> You still need to initialize all the UART clocks in init_table[]. This ... > Yes. The parent relationships still need to be defined. But I think that's > the only thing we actually need to define still?
You might want to explicitly set the rate too, if there is a divider in the clk module that affects it. If not, then parenting is indeed all you need. > Also the parent relationships > can be board specific I think in some cases, so maybe we want to move those to > DT as well at some point? Yes, that's the plan. I think/thought Prashant was planning to work on that. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
