On Thu, Feb 14, 2013 at 06:30:39PM +0100, Stephen Warren wrote: > On 02/14/2013 03:01 AM, Peter De Schrijver wrote: > > On Wed, Feb 13, 2013 at 05:48:03PM +0100, Stephen Warren wrote: > ... > >> You still need to initialize all the UART clocks in init_table[]. This > ... > > Yes. The parent relationships still need to be defined. But I think that's > > the only thing we actually need to define still? > > You might want to explicitly set the rate too, if there is a divider in > the clk module that affects it. If not, then parenting is indeed all you > need.
Yes, for PLLs that might be useful. Device clock rates can also be set by the driver and probably should be set by the driver. Cheers, Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
