On 05/30/2014 05:20 AM, Hiroshi Doyu wrote: > The later Tegra SoC(>= T124) has more registers for > MC_SMMU_TRANSLATION_ENABLE_*. Now those info is provided as platfrom > data. If those varies a lot on SoCs in the future, we can consider > putting them into DT later.
> diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt > b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt > Required properties: > -- compatible : "nvidia,tegra30-smmu" > -- reg : Should contain 3 register banks(address and length) for each > +- compatible : "nvidia,tegra124-smmu", "nvidia,tegra30-smmu" > +- reg : Can contain multiple register banks(address and length) for each > of the SMMU register blocks. How many is "multiple"? This seems like rather a weak definition of how many entries are expected. What are the different register banks? -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
