Le Fri, Oct 10, 2025 at 05:38:37PM +0200, Valentin Schneider a écrit : > Deferring kernel range TLB flushes requires the guarantee that upon > entering the kernel, no stale entry may be accessed. The simplest way to > provide such a guarantee is to issue an unconditional flush upon switching > to the kernel CR3, as this is the pivoting point where such stale entries > may be accessed. > > As this is only relevant to NOHZ_FULL, restrict the mechanism to NOHZ_FULL > CPUs. > > Note that the COALESCE_TLBI config option is introduced in a later commit, > when the whole feature is implemented. > > Signed-off-by: Valentin Schneider <[email protected]> > --- > arch/x86/entry/calling.h | 26 +++++++++++++++++++++++--- > arch/x86/kernel/asm-offsets.c | 1 + > 2 files changed, 24 insertions(+), 3 deletions(-) > > diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h > index 813451b1ddecc..19fb6de276eac 100644 > --- a/arch/x86/entry/calling.h > +++ b/arch/x86/entry/calling.h > @@ -9,6 +9,7 @@ > #include <asm/ptrace-abi.h> > #include <asm/msr.h> > #include <asm/nospec-branch.h> > +#include <asm/invpcid.h> > > /* > > @@ -171,8 +172,27 @@ For 32-bit we have the following conventions - kernel is > built with > andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg > .endm > > -.macro COALESCE_TLBI > +.macro COALESCE_TLBI scratch_reg:req > #ifdef CONFIG_COALESCE_TLBI > + /* No point in doing this for housekeeping CPUs */ > + movslq PER_CPU_VAR(cpu_number), \scratch_reg > + bt \scratch_reg, tick_nohz_full_mask(%rip) > + jnc .Lend_tlbi_\@
I assume it's not possible to have a static call/branch to take care of all this ? Thanks. -- Frederic Weisbecker SUSE Labs
