> I'm all for fixing the slab allocator to allocated from non-cachedJust a riminder that we also need to get rid of bus_to_virt().
> memory (heh, trust me - don't look at usb-ohci-sa1111.h :-)Sorry -- already did! :) There's a MIPS patch too; I hope to
start fixing this soon "for real".
The MIPS implementation of pci_alloc_consistent() returns pages
in kseg1
(the unmapped, unchached kernel seg). But bus_to_virt() converts
to kseg0
addresses (unmapped, cached). So now a TD that was allocated from
kseg1
is recovered in dl_done_list() pointing to kseg0. So we're mixing cached
and
uncached pointers, and it becomes very difficult knowing whether a
pointer needs
flushing or not (ie. is it a cache consistent buffer or not?). An obvious
solution
would be to change the MIPS implementation of bus_to_virt() to
return a kseg1
address, but this could break all kinds of stuff. Anyway, bus_to_virt
will be obsoleted.
As a replacement for bus_to_virt(), how about using a hash table? Ie.,
when
allocating a TD, use the TDs bus address to form an index into a virtual
address
table. But maybe a bus-to-virt hash table should be a kernel service
(is this
already in the works as a bus_to_virt() replacement?).
One other thing for cache incoherent systems: urb->transfer_buffer
(which is the
TDs payload pointer) needs to be written-back and invalidated before
the TD is
submitted. The MIPS patch is already doing this.
> but, shouldn't a distinction be made between hardware cache alignment
> and strict hardware required alignment?Well, the specs for kmem_cache_create() say that when you
pass that flag, it gives you cache-aligned data -- period, end
of story. I think you're talking about that as being what I'd
call a "performance hint" ... which is _not_ what's specified.- Dave
> >(1) CONFIG_SLAB_DEBUG breaks the documented
> >requirement that the slab cache return adequately aligned
> >data ... which the appended patch should probably handle
> >nicely (something like it sure did :-) and with less danger
> >than the large patch you posted.
> >
> >
> >--- slab.c-orig Tue Mar 6 15:01:26 2001
> >+++ slab.c Tue Mar 6 15:05:58 2001
> >@@ -676,12 +676,10 @@
> > }
> >
> > #if DEBUG
> >+ /* redzoning would break cache alignment requirements */
> >+ if (flags & SLAB_HWCACHE_ALIGN)
> >+ flags &= ~SLAB_RED_ZONE;
> > if (flags & SLAB_RED_ZONE) {
> >- /*
> >- * There is no point trying to honour cache alignment
> >- * when redzoning.
> >- */
> >- flags &= ~SLAB_HWCACHE_ALIGN;
> > size += 2*BYTES_PER_WORD; /* words for redzone */
> > }
> > #endif
> >
> >
> >
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>
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-- Steve Longerbeam MontaVista Software, Inc. office:408-328-9008, fax:408-328-9204 http://www.mvista.com
