Steve,
Yes, typo -- that was the whole point! :)
And thanks for your help in making this all happen.
- Dave
----- Original Message -----
From: "Steve Longerbeam" <[EMAIL PROTECTED]>
To: <[EMAIL PROTECTED]>
Cc: <[EMAIL PROTECTED]>
Sent: Monday, April 02, 2001 9:37 AM
Subject: Re: [linux-usb-devel] PCI/CPU cache coherency
> David Brownell wrote:
>
> > > I'm trying to use USB driver on a SH4 architecture (SH7750 overdrive
> > > board). The driver code assumes PCI/CPU cache coherency which is not the
> > > case on SH4.
> > > Has anyone already done this work for another architecture?
> > > Does ohci-0323 and pcipool-0323 patches solve this problem?
> > > Are there other additional patches to add?
> >
> > Also add "ohci64-0324.patch" (attached); that should solve the
> > rest of the problem. It's been confirmed to work on a few MIPS
> > machines that use cache-coherent DMA; I'd like to know that it
> > works on your SH4 setup too!
>
> Hi Dave,
>
> I think you meant to say it's been tested on a few MIPS machines that
> are *not* DMA cache coherent.
>
> Steve
>
> >
> >
> > > On overdrive there is a restriction doing DMA across PCI. We can only
> > > DMA from memory behind the PCI bus, so all the DMA' able memory must
> > > come from there. The USB controller manipulates lists of descriptors
> > > that are located in RAM and requires DMA access to these descriptors.
> > > How can I support the driver's ability to allocate these lists on
> > > memory behind PCI bus (PCI DRAM non cacheable).
> >
> > That much is what the "ohci-0323" patch does. But there's a bit
> > more needed too ... getting rid of bus_to_virt calls, and managing
> > single shot DMA mappings for the transfer and setup buffers.
> > That's what the ohci64-0324 patch does.
> >
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