>[...]
> OHCI is a silicon which works with a high-speed, DMA master bus.
> Adaptations of the IP block to ARM exist, but primarily it is
> sold as a PCI master. How are you going to hook it to ISA?
BTW, I'm not saying it cannot be done. If you are willing
to do a little bit of design, you can use a dual-port
memory for rate adaptation:
ISA => ISA master => controller => OHCI IP block from ARM => USB
||
DRAM
May even fit an FPGA. Or, you can just hook existing chips together:
ISA => ISA slave, 2 mailbox => PCI bus => COTS OHCI => USB
registers, & PCI slave ||
CPU w/ PCI arbiter
(PPC 8260 or microSPARC-IIep)
has built-in DRAM controller
||
DRAM
The problem is that either way it's going to cost a fortune,
and be slow. Big fortune and slow in the first case, and
smaller fortune and slow like molasses in the second case.
-- Pete
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