On Wed, Feb 04, 2004 at 10:07:03AM +0100, [EMAIL PROTECTED] wrote:
> Hello all,
> you might think I am crazy but my aim is to get a usb-driver for rtai,
> as there is none. I have only a cpia camera there to test.(P3, 2.4.21)
> Now I am trying to understand the usb subsystem as a whole. Newbie, who
> am i, I have read _anything_ related to the usb-core, like the usb
> Programming guide reference list, uhci.txt
> Unfortunately I found nothing like "Understanding the linux kernel- usb
> subsystem".
First I must say I'm a USB newbie, too (I'm trying to get the SL811
USB host cheip running with 2.6).
For me, reading the USB 1.1 specs did help a bit. Then I read the
source of the OHCI host code, a bit of the generic host code and
_some_ of the questions vanished (more did arise, though ;)
> So I dare to ask you for some tips on implementation details or some
> resources that I did not know yet. Which method would you advise to
> understand best what is going on?
> Now you see me figuring out which codepaths are there, which
> usb-synchronisation mechanisms are used...
> Finally I got stuck by the question how does the usb transfer take
> place.
> Sure, "queue_urb" puts the urb in the list of pending urbs, and in the
> interrupt routine thread "process_urb" picks them up, but here is where
> I loose track.
If I understand correctly, those URBs are broken up un "TD" -- Transfer
Descriptors -- which are then being transfered. Exactly how this is done
seems Host Controller specific (UHCI, OHCI and so on).
The other thing to notice is, that communication is initiated only from the
host, even for IN transfers as it seems. The USB specs have nice state diagrams
showing the transfer types possible.
All communtcation is done in certain time slots ("frames"), and the host
controllers schedule what communtication is done in what frame (read: what TD
is to be sent in which frame); they do some sort of "load balancing" wrt USB
bandwith. Each Host Controller does this differently, as it seems (that's why
there are these lists of TDs and such).
What I did not found out yet is how the Host actually transmits TDs, that is, how do
the TDs get from CPU memory to the Hoct Controller.
Just my 2 cents, though.
> Where in particular is the point where hcd says to hc: now do transfer!?
> How are the synchronisation mechanisms implemented in this context?
> Even if you do not or do not want to answer these details, any
> suggestions, comments are welcome.
>
> Thanks
> Thomas Feldburg
>
>
>
>
>
>
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