> > Sounds like there are still delays missing. > Yeah, it does. A 1 micro-second delay should do it, right? I've also run into trouble with how picky the chip is. For instance, the chip select and read signal must be deasserted between reads. (see Fig. 31, pg 137 of the ISP1362 manual) If I just don't write, it sometimes leaves chip-select asserted. So, I can write to another chip select in the mean-time to force it to change.
Also, the read and write lines should be gated on the chip-select. It's kinda picky in that way. If you haven't seen it, there's an errata here: http://www.semiconductors.philips.com/acrobat_download/other/usb/ISP1362_Errata_040527.pdf (the link on their ISP1362 page is broken, but i was able to find it) Make sure your bus timing and such is correct. We've had trouble with this. I think ours is okay now. Mike ------------------------------------------------------- This SF.Net email is sponsored by: InterSystems CACHE FREE OODBMS DOWNLOAD - A multidimensional database that combines robust object and relational technologies, making it a perfect match for Java, C++,COM, XML, ODBC and JDBC. www.intersystems.com/match8 _______________________________________________ [EMAIL PROTECTED] To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
