On Friday 22 April 2005 10.46, Lothar Wassmann wrote: > Robin Farine writes:
> > I think you also need to actually use the result of the read to > > force a previous store operation to terminate. And I wonder if > > Nope. The "volatile" attribute makes sure that the access is > actually done. I did not mean that the compiler was optimizing the read access out, but rather that the CPU might not complete a pending store to isp chip until the target operand of the read from the uncached location is actually used as source operand, thus the "mov %1, %1" in my version. At least that is what I understand from "Intel® PXA26x Processor Family Developer's Manual, 2.4 Input/Output Ordering". > I'm getting ~700ns delay with the UNCACHED_PHYS_0 access alone. OK then, but this has to be verified with a scope for each platform since e.g. on a PXA with a 100Mhz memory clock, an uncached read from SDRAM can theoretically take ~70ns right? Robin ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. Start reading now. http://ads.osdn.com/?ad_ide95&alloc_id396&op=click _______________________________________________ linux-usb-devel@lists.sourceforge.net To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
